FW802B-DB LSI, FW802B-DB Datasheet - Page 8

• Manufacturer Part Number: FW802B-DB
• Manufacturer: LSI

Specifications of FW802B-DB

• Lead Free Status / Rohs Status: Not Compliant

FW802B Low-Power PHY IEEE 1394A-2000
Two-Cable Transceiver/Arbiter Device
Signal Information
Table 1. Signal Descriptions (continued)
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
8 8
44, 45, 46,
47, 48
Pin
23
16
20
21
22
19
57
58
54
55
1
V
V
Signal*
LREQ
DD
SS
/ISO
PC0
PC1
PC2
LPS
NC
PD
R0
R1
PLL
PLL
(continued)
Type
—
—
—
I
I
I
I
I
I
Link Interface Isolation Disable Input (Active-Low). /ISO controls the
operation of an internal pulse differentiating function used on the
PHY-LLC interface signals, CTLn and Dn, when they operate as outputs.
When /ISO is asserted low, the isolation barrier is implemented between
PHY and its LLC (as described in Annex J of IEEE 1394-1995).
/ISO is normally tied high to disable isolation differentiation. Bus-keepers
are enabled when /ISO is high (inactive) on CTLn, Dn, and LREQ. When
/ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note IEEE 1394 Isolation (AP98-074CMPR) for more informa-
tion.
Link Power Status. LPS is connected to either the V
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2 µs and less than 25 µs, the PHY-link interface is reset. If LPS is
inactive for greater than 25 µs, the PHY will disable the PHY/link interface
to save power. FW802B continues its repeater function.
Link Request. LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
No Connect.
Powerdown. When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW802B logic is
kept in the reset state as long as PD is asserted. The PD terminal is
provided for backward compatibility. It is recommended that the FW802B
be allowed to manage its own power consumption using suspend/resume
in conjunction with LPS. C/LKON features are defined in the IEEE 1394a-
2000 specification.
Power for PLL Circuit. V
portion of the device.
Ground for PLL Circuit. V
plane.
Current Setting Resistor. An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ ± 1% should be used to meet the
IEEE 1394-1995 standard requirements for output voltage limits.
Power-Class Indicators. On hardware reset (/RESET), these inputs set
the default value of the power class indicated during SelfID. These bits can
be tied to V
consumption and source characteristics. In SelfID packet (see Section
4.3.4.1 of the 1394a-2000 Specification), PC0, the most significant bit of
this 3-bit field, corresponds to bit 20, PC1 corresponds to bit 21, and PC2
corresponds to bit 22. As an example, for a Power_Class value of 001,
PC0 = 0, PC1 = 0, and PC2 = 1.
DD
(high) or to ground (low) as required for particular power
DD
Name/Description
SS
PLL supplies power to the PLL circuitry
PLL is tied to a low-impedance ground
Data Sheet, Rev. 3
DD
Agere Systems Inc.
supplying the
May 2004