LM49450SQ/NOPB National Semiconductor, LM49450SQ/NOPB Datasheet - Page 28

IC AUDIO SUBSYSTEM 2.5W D 32LLP

LM49450SQ/NOPB

Manufacturer Part Number
LM49450SQ/NOPB
Description
IC AUDIO SUBSYSTEM 2.5W D 32LLP
Manufacturer
National Semiconductor
Series
Boomer®r
Type
Class Dr
Datasheet

Specifications of LM49450SQ/NOPB

Output Type
2-Channel (Stereo) with Stereo Headphones
Max Output Power X Channels @ Load
2.5W x 2 @ 4 Ohm
Voltage - Supply
2.7 V ~ 5.5 V
Features
3D, DAC, Depop, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Shutdown, Volume Control
Mounting Type
Surface Mount
Package / Case
32-LLP
Amplifier Class
D
No. Of Channels
2
Output Power
1.2W
Supply Voltage Range
2.7V To 5.5V
Load Impedance
8ohm
Operating Temperature Range
-40°C To +85°C
Amplifier Case Style
LLP
Rohs Compliant
Yes
For Use With
LM49450SQEVAL - BOARD EVAL FOR LM49450
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LM49450SQ
LM49450SQ
LM49450SQTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM49450SQ/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
www.national.com
CHARGE PUMP CLOCK REGISTER (0x02h)
The charge pump clock register sets the charge pump fre-
quency derived from MCLK when the LM49450 is in DAC
mode. Default value is for register 02h is 0x49h.
CP_DIV REGISTER
LM49450 Clock Structure
This register is used to control the charge pump clock when
the register field LINE_IN_ENABLE is low i.e. DAC mode.
Examples of CP_DIV Values one might use for various
sample rates and DAC modes
B7:B0
Bit
CPDIV_7
CPDIV_6
CPDIV_5
CPDIV_4
CPDIV_3
CPDIV_2
CPDIV_1
CPDIV_0
Name
Bits
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
7:0
MCLK (MHZ)
2.75625
5.5125
2
3
4
6
8
B7
0
0
0
0
0
0
1
1
1
B6
0
0
0
0
0
0
1
1
1
TABLE 8. Typical CP_DIV Values for DAC Mode 00
CP_DIV
TABLE 6. Charge Pump Clock Register
TABLE 7. CP_DIV Default Value 0x49h
B5
Field
0
0
0
0
0
0
1
1
1
TO
B4
0
0
0
0
0
0
1
1
1
Value
CP_DIV
11
16
17
23
33
36
48
B3
28
0
0
0
0
0
0
1
1
1
Programs the CP divider (devides from an expected 12.000MHz
When the register field LINE_IN_ENABLE is high, the Clocks
module is held in reset and as a result no CP_CLOCK_C is
produced.
B2
0
0
0
0
1
1
1
1
1
CP_DIV
5 to 253
254
255
0
1
2
3
4
B1
0
0
1
1
0
0
0
1
1
Description
B0
0
1
0
1
0
1
1
0
1
input).
Nominal Frequency (Hz)
Sets charge pump oscillator
frequency in DAC mode
(derived from MCLK).
333333
324265
333333
333333
324264
324324
326530
In 0.5 increments
Bypass divider
Divide Value
Description
3 to 127
Bypass
127.5
127.5
128
127
128
1.5
2.5
1.5
2.5
1
2
1
2
3

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