MT47H64M16HR-3 L:HTR Micron Technology Inc, MT47H64M16HR-3 L:HTR Datasheet - Page 132
MT47H64M16HR-3 L:HTR
Manufacturer Part Number
MT47H64M16HR-3 L:HTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H64M16HR-3_LHTR.pdf
(136 pages)
Specifications of MT47H64M16HR-3 L:HTR
Lead Free Status / Rohs Status
Compliant
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MRS Command to ODT Update Delay
Figure 81: Timing for MRS Command to ODT Update Delay
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Notes:
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command.
R
Command
Command
TT
Address
Internal
1. The LM command is directed to the mode register, which updates the information in
2. To prevent any impedance glitch on the channel, the following conditions must be met:
setting
ODT 2
ODT
CK#
CKE
CK#
R
CK
CK
TT
EMR (A6, A2), that is, R
t
tire duration of the
AOFD must be met before issuing the LM command; ODT must remain LOW for the en-
Valid
Valid
T0
T0
Old setting
t AOFD
t CK
EMRS 1
Ta0
Valid
Valid
T1
t
t CH
0ns
MOD window until
TT
132
(nominal).
t CL
t AON (MIN)
t AOND
Ta1
NOP
Valid
Valid
t AON (MAX)
T2
t MOD
t
MOD (MAX) updates the R
Undefined
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
Ta2
Valid
Valid
T3
t AOFD
t
MOD is met.
R
TT
1Gb: x4, x8, x16 DDR2 SDRAM
Unknown
NOP
Ta3
Valid
Valid
T4
t IS
t AOF (MIN)
R
2
Ta4
NOP
Valid
Valid
TT
T5
2007 Micron Technology, Inc. All rights reserved.
t AOF (MAX)
On
New setting
Indicates a break in
time scale
TT
setting.
NOP
Ta5
Valid
Valid
Don’t Care
T6
ODT Timing
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