MT47H64M16HR-3 L:HTR Micron Technology Inc, MT47H64M16HR-3 L:HTR Datasheet - Page 83
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MT47H64M16HR-3 L:HTR
Manufacturer Part Number
MT47H64M16HR-3 L:HTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H64M16HR-3_LHTR.pdf
(136 pages)
Specifications of MT47H64M16HR-3 L:HTR
Lead Free Status / Rohs Status
Compliant
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CAS Latency (CL)
Figure 36: CL
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. W 7/11 EN
Notes:
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 35 (page 80). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may re-
sult.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to
nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further
detail in Posted CAS Additive Latency (AL) (page 86).
Examples of CL = 3 and CL = 4 are shown in Figure 36; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
DQS, DQS#
DQS, DQS#
Command
Command
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
NOP
NOP
T1
T1
CL = 3 (AL = 0)
t
AC,
83
t
DQSCK, and
CL = 4 (AL = 0)
NOP
NOP
T2
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
NOP
NOP
T3
T3
1Gb: x4, x8, x16 DDR2 SDRAM
DO
n
t
RCD (MIN) by delaying the inter-
n + 1
DO
NOP
NOP
T4
T4
Mode Register (MR)
n + 2
DO
DO
n
2007 Micron Technology, Inc. All rights reserved.
Transitioning data
n + 1
n + 3
DO
DO
NOP
NOP
T5
T5
n + 2
DO
n + 3
DO
NOP
NOP
Don’t care
T6
T6
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