LC7471 Sanyo Semiconductor Corporation, LC7471 Datasheet
LC7471
Available stocks
Related parts for LC7471
LC7471 Summary of contents
Page 1
... The LC7471 features selectable pixel width and pixel height, and 64 vertical and 64 horizontal display start posi- tions. It also features a flashing enable bit for each charac- ter position. The LC7471 operates from supply and is available in 22-pin shrink DIPs. Features • Complete text and graphics video overlay circuitry. ...
Page 2
... Block Diagram LC7471 No.4088–2/12 ...
Page 3
... Pin Description Specifications Absolute Maximum Ratings Reommended Operating Conditions 25˚ Electrical Characteristics –30 to +70˚ LC7471 25˚ 5V, unless otherwise noted DD1 – – – – – – – No.4088–3/ ˚C 5 ˚ µ µ µ A ...
Page 4
... A 16-bit address word followed by 16-bit data words is input after the falling edge of CS. The address automati- Only the lower eight bits of the address word are signifi- cant. Only the lower eight bits of data words at addresses 000H to 0AFH, the lower 11 bits of data words at LC7471 = 5 0.5V DD1 S y ...
Page 5
... The function of each bit in the horizontal display control register is shown in the following table. Note that a LOW- level pulse on RST resets all bits – Table 1. Line 1 pixel width LC7471 address registers, locations 0BCH to 0BDH are display con- trol registers, location 0BEH is the video signal control reg- ister and location 0BFH is the general control register ...
Page 6
... The function of each bit in the vertical display control register is shown in the following table. Note that a LOW-level pulse on RST resets all bits – Table 4. Line 1 pixel height The relationships between the vertical sync and horizon- tal sync pulses and between the horizontal and vertical display start positions are shown in the following figure. LC7471 Table 5. Line 2 pixel height ...
Page 7
... – – Table 7. Phase selection General Control Register (0BFH) The function of each bit in the general control register is shown in the following table. Note that a LOW-level pulse on RST resets all bits – – – – – Table 8. Flashing duty cycle selection LC7471 ...
Page 8
... LC7471 code in ROM is ignored and the character code is read from display RAM. The display RAM address automati- cally increments by one each time a character code is read from RAM. Note that your local SANYO representative can offer advice on how to specify the generator character ROM ...
Page 9
... The start address for each of the twelve display lines is specified in the display line address registers in RAM. An example arrangement of ROM and RAM addresses is shown in the following table. Note how both the RAM and ROM addresses increment LC7471 24 characters, making a maximum number of 288 characters ...
Page 10
... The character and background images are superimposed onto the composite video signal. The composite video signal output levels when the sync pulse level is 1.2V and V ing figure and the voltages corresponding to the relative carrier amplitudes in the following table – – LC7471 ...
Page 11
... The composite video signal output levels when the sync pulse level is 1.2V and V ing figure, and the voltages corresponding to the relative carrier amplitudes in the following table – – LC7471 =5.000V are shown in the follow- DD No.4088–11/12 ...
Page 12
... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of August, 2001. Specifications and information herein are subject to change without notice. LC7471 PS No.4088–12/12 ...