LC74776 Sanyo Semiconductor Corporation, LC74776 Datasheet
LC74776
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LC74776 Summary of contents
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... Ordering number : EN*6018 Preliminary Overview The LC74776 on-screen display controller CMOS IC that displays characters and patterns on the TV screen under microprocessor control. This IC includes a built-in PDC/VPS/UDT interface circuit. Functions • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) 18 (vertical) dots • ...
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... Pin Assignment LC74776, 74776M LC74776 LC74776M No. 6018-2/35 ...
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... Power supply (+ Note: *Both V 1 pins must be connected to power. DD LC74776, 74776M Notes Ground connection (digital system ground) These pins are used either to connect the crystal and capacitors used to form an external crystal oscillator circuit to generate the internal synchronizing signals input an external clock signal (2fsc or 4fsc mask option, the Xtal the MUTE input pin ...
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... Note: Applications must be especially cautious about noise when using the Xtal Electrical Characteristics –30 to +70°C, V Paremeter Input off leakage current Output off leakage current Output high-level voltage Output low-level voltage Three-value output voltage Input current Operating mode current drain SYNC level Pedestal level LC74776, 74776M Symbol Conditions V max and ...
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... Blue background color 1 and 2 high level Frame level 0 Frame level 1 Character level Notes: (1): When the sync level = 0.8 V (2): When the sync level = 1.0 V (3): When the sync level = 1.4 V The blue background color ( set as an option. LC74776, 74776M Symbol Conditions 5.0V, OUT DD V ...
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... PDC/VPS Write and Read (I C timing) Paremeter SCL frequency Bus release time Start/hold SCL low-level period SCL high-level period Data hold Data setup Rise time Fall time Stop/setup LC74776, 74776M ±0 Symbol Conditions t (SCLK) SCLK W t (CS) CS (The period when CS is high) W ...
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... LC74776, 74776M Figure 1 OSD Serial Data Input Timing S: Start condition P: Stop condition Figure 2 PDC/VPS Serial Timing ( bus) No. 6018-7/35 ...
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... System Block Diagram LC74776, 74776M No. 6018-8/35 ...
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... LC74776/M locks into the display character data write mode, and another first byte cannot be written. When the CS pin is set high, the LC74776/M is set to the COMMAND0 (display memory write address setup mode) state. LC74776, 74776M (the SCL and SDA pins) ...
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... Register State 7 – – – Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. COMMAND1 (Display character data write setup command) • First byte Register State 7 – – – – – – – – 0 LC74776, 74776M Contents Function Command 0 identification code ...
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... Register State Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. COMMAND2: Vertical display start position and vertical character size setup command • First byte Register State 7 – – – – VS21 VS20 VS11 VS10 1 • Second byte ...
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... HP3 HP2 HP1 1 HP0 0 0 (LSB) 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 3 identification code. Horizontal display start position and the horizontal character size setup. VS20 0 VS21 0 1Tc/dot 1 3Tc/dot VS10 ...
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... DSPON 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 4 identification code. Display character data write setup. Normal operating mode Test mode Erase display RAM.(The RAM data is set to FF hexadecimal.) Do not stop the crystal and LC oscillators ...
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... PH2 PH1 PH0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 5 identification code. Display control setup. NTSC PAL 525 lines 625 lines Interlaced Noninterlaced External synchronization Internal synchronization Contents Function Second byte identification bit Background color level 1 ...
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... RN0 SN3 SN2 SN1 SN0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 6 identification code. Synchronizing signal control setup. SEL0 MOD0 SEPOUT 0 0 DAV 0 1 Sliced data width 1 0 CSYNC 1 1 ...
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... MSKERS MSKSEL EGL 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 0 identification code Contents Function Second byte identification bit Blank area (The logical OR of the character and frame signals) ...
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... LPA2 LPA1 LPA0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 1 identification code Contents Function Second byte identification bit LNA3 LNA2 LNA1 LNA0 Specified line ...
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... LPB2 LPB1 LPB0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 2 identification code Contents Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 Specified line ...
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... LPC2 LPC1 LPC0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 3 identification code Contents Function Second byte identification bit LNB3 LNB2 LNB1 LNB0 Specified line ...
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... MOD3 LNBSEL MOD2 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 4 identification code Contents Function Second byte identification bit LC oscillator: operating LC oscillator: stopped ...
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... SEL2 OTHS IND3 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command 5 identification code Contents Function Second byte identification bit OTDS1 OTDS0 Dot clock ...
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... SJNS1 SJCS1 SJCS0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M Contents Function Command 7 identification code. Display control setup. Extended command B identification code Contents Function Second byte identification bit Sync discrimination signal absent present: normal value ...
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... VPM2 VPM1 VPM0 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M 2 C bus only Contents Function Command 7 identification code. Display control setup. Extended command 5 identification code Contents Function Second byte identification bit CPA2 ...
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... BMS EMS DCE 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M 2 C bus only Contents Function Command 7 identification code. Display control setup. Extended command 6 identification code Contents Function Second byte identification bit V mask period start - From the retrace period ...
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... ECV12 ECV11 ECV5 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M 2 C bus only Contents Function Command 7 identification code. Display control setup. Extended command 7 identification code Contents Function Second byte identification bit Byte 15 biphase error check on (Data hold) ...
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... ECP15 ECP14 ECP13 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M 2 C bus only Contents Function Command 7 identification code. Display control setup. Extended command 8 identification code Contents Function Second byte identification bit Byte 19 Hamming error check on (Data hold) ...
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... ECP22 ECP21 ECP20 1 Note: All registers are set to 0 when the LC74776/M is reset by the RST pin. LC74776, 74776M 2 C bus only Contents Function Command 7 identification code. Display control setup. Extended command 9 identification code Contents Function Second byte identification bit Byte 25 Hamming error check on (Data hold) ...
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... Byte 2 Bit 7 byte 16 bit Byte 3 Bit 7 byte 17 bit Byte 4 Bit 7 byte 18 bit Byte 5 Bit 7 byte 19 bit Byte 6 Bit 7 byte 20 bit LC74776, 74776M VPS mode Format 2 byte 16 bit 0 byte byte17 bit byte 18 bit 0 byte byte19 bit byte 20 bit 0 byte byte 21 bit ...
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... Byte 12 Bit 7 byte 24 bit Byte 13 Bit 7 byte 25 bit Note: A value output for section with no output data setting. LC74776, 74776M VPS mode Format 2 byte 13 bit Error byte 16 Error byte 11 information 1 information Error 14 information Header time mode 1 (3) Header time mode 2 (4) ...
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... Byte 3 Bit 7 byte 28 6 (28 Byte 4 Bit 7 byte 29 6 (29 Byte 5 Bit 7 byte 30 6 (30 Byte 6 Bit 7 byte 31 6 (31 Byte 7 Bit 7 byte 32 6 (32 LC74776, 74776M PAL Puls bit 0 byte 36 bit 0 1 (36 bit 0 byte 37 bit 0 1 (37 bit 0 byte 38 bit 0 1 (38 bit 0 byte 39 bit 0 1 (39) ...
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... Bit 7 byte 35 6 (35 Byte 11 Bit 7 Error information Byte 12 Bit 7 Error information Byte 13 Bit Note: A value output for section with no output data setting. LC74776, 74776M Status display mode 2 (4) bit 0 byte 43 bit 0 1 (43 bit 0 byte 44 bit 0 1 (44 bit 0 byte 45 bit 0 1 (45) ...
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... Up to 288 characters can be displayed. The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are displayed. Display memory addresses are specified as row ( decimal) and column ( decimal) addresses. Display Screen Structure (display memory addresses) LC74776, 74776M 24 Characters No. 6018-32/35 ...
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... V : Blue background color 2: low RSL2 V : Frame 1 BK1 V : Frame 2 BK0 V : Pedestal Color burst low CBL V : Sync SN LC74776, 74776M 2 = 5.00 V) Output voltage (1) [V] 2.65 2.37 2.01 1.67 1.23 1.16 1.52 2.08 1.50 1.37 1.07 0.80 Output voltage (2) [V] Output voltage (3) [V] 2.85 3.25 2 ...
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... Application Circuit Examples (When used connected to a single-chip Y/C circuit) • External system clock input Microcontroller • Crystal oscillator Microcontroller LC74776, 74776M No. 6018-34/35 ...
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... This catalog provides information as of Februaly, 1999. Specifications and information herein are subject to change without notice. LC74776, 74776M must be connected with the correct polarity when a sync tip level of IN input video signal pedestal level will be clamped to about 2.5 V. ...