LB1823 Sanyo Semiconductor Corporation, LB1823 Datasheet
LB1823
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LB1823 Summary of contents
Page 1
... A motor driver circuit with the desired output power (current and voltage) can be constructed by attaching either a driver array or discrete components at the output. The LB1823 output supports direct PWM drive and thus allows the implementation of low-loss drive circuits. Additionally, the LB1823 includes several associated circuits, such as a speed control circuit, and FG amplifier, and an integrating amplifier, on chip ...
Page 2
... Amplitude V (CR) [Current Limiter Operation] Limiter V RF [Thermal Shutdown Operation] Thermal shutdown operating TSD temperature ∆TSD Hysteresis [V Pin] REG V pin voltage V REG REG LB1823 Symbol Conditions V max pin REG REG I UL, VL and WL outputs O Pd max Topr Tstg Symbol Conditions I V pin (7 V) ...
Page 3
... IH (F/R) Input low level voltage V IL (F/R) ∆V Hysteresis IN Pull-down resistor R D (F/R) [BR Pin] Input high level voltage V IH (BR) Input low level voltage V IL (BR) ∆V Hysteresis IN Pull-down resistor R D (BR) LB1823 Conditions Gain: 100 kHz (FG (FGS Crystal oscillator External signal input min ...
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... Pin Assignment Block Diagram LB1823 No. 4263-4/11 ...
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... F Item IN1 IN2 IN3 Note: High (H) for a given input (IN) specifies the state where IN The formula below gives the relationship between the crystal oscillator frequency (f f (servo /(ECL16 divisor number of counts) FG OSC = f /8192 OSC LB1823 F Output IN1 IN2 IN3 Source Sink – ...
Page 6
... Forward/reverse control 2 F/R Low or open for forward, high for reverse Brake, short brake 3 BR Low or open for start, high for brake. The S/S pin must be set to the stop state when releasing the brake. LB1823 External Constants (reference value, V Xtal (MHz) C1(pF ...
Page 7
... Notes on LB1823 Operation and External Components 1. Speed control circuit The LB1823 uses a speed discriminator circuit and a PLL circuit in combination for speed control. The speed discriminator generates an error output once every two FG periods using a charge pump technique. The PLL circuit generates a phase error output once every FG period, also using a charge pump technique. By using a speed discriminator circuit and a PLL circuit together, the LB1823 can suppress speed variations better than earlier systems that only used a speed discriminator for speed control when used with motors faced with large load variations ...
Page 8
... The speed lock range is ±6.25% of the rated speed, and the LD pin (which is an open collector output) will be low when the motor speed is within the lock range. The LB1823 controls the motor speed to be within the lock range by generating a speed error signal when the motor speed goes out of the lock range and adjusting the motor drive on duty according to that signal ...
Page 9
... OUT h min: Output transistor minimum current amplification factor FE V sat: The LB1823 output saturation voltage O • R16 R16 sets the shunt regulator bias current. R16 must be selected so that a current of over 1 mA flows in the V voltage range for which guaranteed correct operation is desired. ...
Page 10
... Oscillator element Normally, a crystal resonator, a resistors, and two capacitors are connected to the LB1823 Xtal pin. A ceramic oscillator could also be used in applications that do not require such precise speed control characteristics. To avoid problems, consult with the manufacturer of the oscillator element when selecting the oscillator element and the values of the external resistor and capacitors used ...
Page 11
... This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice. LB1823 and INT. (R4) is too small, the values of C6 and C7 will become large. ...