HMS87C1202A Hynix Semiconductor, HMS87C1202A Datasheet
HMS87C1202A
Available stocks
Related parts for HMS87C1202A
HMS87C1202A Summary of contents
Page 1
Apr. 2001 8-BIT SINGLE-CHIP MICROCONTROLLERS HMS87C1304(2)A HMS87C1204(2)A HMS87C1104(2)A User’s Manual Ver 1.0 ...
Page 2
OVERVIEW ....................................................................................................................... 1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
HMS87C130XA/120XA/110XA 12.2 16-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
... HMS87C1304A / HMS87C1302A HMS87C1204A / HMS87C1202A HMS87C1104A / HMS87C1102A CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER 1. OVERVIEW 1.1 Description The HMS87C1X0XA is an advanced CMOS 8-bit microcontroller with 4K/2K bytes of EPROM. The Hynix HMS87C1X0XA is a powerful microcontroller which provide a highly flexible and cost effective solution to many small applications such as controller for battery charger. The HMS87C1X0XA provides the following standard features: 4K/2K bytes of EPROM, 128bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, power-on reset circuit, on-chip oscillator and clock circuitry ...
Page 5
HMS87C130XA/120XA/110XA • Oscillator Type - Crystal - Ceramic Resonator - RC-oscillation ( C can be omitted ) • Power-On Reset 1.3 Development Tools The HMS87C1X0XA is supported by a full-featured mac- ro assembler, an in-circuit emulator CHOICE-Dr OTP programmers. The ...
Page 6
... Apr. 2001 ver1.0 Package Type Ordering Device Code 24 SKDIP HMS87C1304A SK 24 SOP HMS87C1304A D 20 PDIP HMS87C1204A 20 SOP HMS87C1204A D 16 PDIP HMS87C1104A 16 SOP HMS87C1104A D 24 SKDIP HMS87C1302A SK 24 SOP HMS87C1302A D 20 PDIP HMS87C1202A 20 SOP HMS87C1202A D 16 PDIP HMS87C1102A 16 SOP HMS87C1102A D HMS87C130XA/120XA/110XA Operating Temperature - ...
Page 7
HMS87C130XA/120XA/110XA 2. BLOCK DIAGRAM PSW RESET System controller System Clock Controller Timing generator X IN Clock Generator X OUT Watch-dog Timer Power Supply † Note These pins are not available in HMS87C1204(2)A. ‡ These pins are ...
Page 8
PIN ASSIGNMENT HMS87C1304(2 SKDIP AN4 / RA4 1 AN5 / RA5 2 AN6 / RA6 3 AN7 / RA7 RD0 6 RD1 7 8 AN0 / AV / RB0 REF 9 BUZ / ...
Page 9
HMS87C130XA/120XA/110XA 4. PACKAGE DIAGRAM 24 SKDIP 0.021 0.015 24 SOP 0.614 0.593 0.019 0.0138 6 1.265 1.160 0.065 TYP 0.100 0.045 TYP 0.050 unit: inch MAX MIN TYP 0.300 0.300 0.250 0 ~ 15° 8° 0.042 0.016 Apr. ...
Page 10
PDIP 0.021 0.015 20 SOP 0.020 0.013 Apr. 2001 ver1.0 1.043 1.010 0.065 TYP 0.100 0.050 0.5118 0.4961 TYP 0.050 HMS87C130XA/120XA/110XA unit: inch MAX MIN TYP 0.300 0.270 0.245 0 ~ 15° 8° 0.042 0.016 7 ...
Page 11
HMS87C130XA/120XA/110XA 16 PDIP 0.765 0.745 0.022 0.015 16 SOP 0.019 0.014 8 0.065 TYP 0.100 0.050 0.412 0.402 TYP 0.050 unit: inch MAX MIN TYP 0.300 0.260 0.240 0 ~ 15° 8° 0.040 0.016 Apr. 2001 ver 1.0 ...
Page 12
PIN FUNCTION V : Supply voltage Circuit ground RESET: Reset the MCU Input to the inverting oscillator amplifier and input to IN the internal main clock operating circuit Output from the ...
Page 13
HMS87C130XA/120XA/110XA PIN NAME 87C1304(2)A 87C1204(2)A 87C1104(2 RESET OUT RA0 (EC0) 21 RA1 (AN1) 22 RA2 (AN2) 23 RA3 (AN3) 24 RA4 (AN4) 1 RA5 (AN5) 2 RA6 (AN6) ...
Page 14
PORT STRUCTURES • RESET Internal RESET • Xin, Xout Crystal or Ceramic STOP To System CLK RC Oscillation (refer to Configuration Area) STOP To System CLK Apr. 2001 ver1.0 HMS87C130XA/120XA/110XA Xout V SS Xin V ...
Page 15
HMS87C130XA/120XA/110XA • RA0/EC0 Data Bus Data Bus Data Bus • RA1/AN1 ~ RA7/AN7 Data Bus Data Bus Data Bus To A/D Converter Analog Input Mode (ANSEL7 ~ 1) Analog CH. Selection (ADCM Open Drain Data Reg. Direction ...
Page 16
RB0 / AN0 / AVref Data Bus AVREFS Data Bus Data Bus To A/D Converter Analog Input Mode (ANSEL0) Analog CH0 Selection (ADCM • RB1/BUZ, RB4/PWM0/COMP0 PWM/COMP BUZ Data Reg. Data Bus Function Select Direction Reg. Data ...
Page 17
HMS87C130XA/120XA/110XA • RB2/INT0, RB3/INT1 Pull-up Select Data Bus Function Select Data Bus Data Bus INT0, INT1 Note: RB3/INT1 pin is not available in HMS87C1104(2)A . • RC0, RD2, RD3 Data Bus Data Bus Data Bus Note: RC0, RD2, RD3 pins ...
Page 18
RC1 Data Bus Data Bus Data Bus • RD0, RD1 Pull-up Select Data Bus Data Bus Data Bus Apr. 2001 ver1.0 Open Drain Data Reg. Direction Reg. Read Data Reg. Direction Reg. Read HMS87C130XA/120XA/110XA Weak ...
Page 19
HMS87C130XA/120XA/110XA 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Supply voltage ........................................... -0.3 to +6.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (V ............................................................... -0 Maximum current out of V pin ...
Page 20
DC Electrical Characteristics (T =-20~ =2.0~5. Parameter Symbol V IH1 V Input High Voltage IH2 V IH3 V IL1 V Input Low Voltage IL2 V IL3 V Output High Voltage OH V Output Low ...
Page 21
HMS87C130XA/120XA/110XA 7.5 AC Characteristics (T =-20~+ =5V 10 Parameter Operating Frequency External Clock Pulse Width External Clock Transition Time Oscillation Stabilizing Time External Input Pulse Width RESET Input Width X IN RESET INT0, INT1 EC0 ...
Page 22
Typical Characteristics This graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified ...
Page 23
HMS87C130XA/120XA/110XA = (mA 0 IH1 X , RESET IN V IH1 f =4MHz XIN (V) Ta= ...
Page 24
R C EXT 10pF 10K 20pF 40pF 10pF 30K 20pF 40pF 10pF 50K 20pF 40pF Table 7-1 RC Oscillation Frequencies (with C Apr. 2001 ver1.0 With External Capacitor OSC OSC EXT 5V,25 C 3V,25 C 4.9MHz 3.94MHz ...
Page 25
HMS87C130XA/120XA/110XA 8. MEMORY ORGANIZATION The HMS87C1X0XA has separate address spaces for Pro- gram memory and Data Memory. Program memory can only be read, not written to. It can 2K/4K bytes of 8.1 Registers This device has six ...
Page 26
NEGATIVE FLAG OVERFLOW FLAG BRK FLAG [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to “0”. This flag immedi- ately becomes “0” when ...
Page 27
HMS87C130XA/120XA/110XA 8.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 4K/2K bytes program memory space only physically implemented. Accessing a location above FFFF will cause a wrap-around to 0000 H ...
Page 28
Address PCALL Area Memory 0FF00 H 0FFFF H PCALL rel 4F35 PCALL 35H 0FF00H 0FF35H NEXT 0FFFFH Apr. 2001 ver1.0 PCALL Area (256 Bytes) Figure 8-6 PCALL and TCALL Memory Area TCALL HMS87C130XA/120XA/110XA ...
Page 29
HMS87C130XA/120XA/110XA Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW NOT_USED DW NOT_USED DW NOT_USED DW BIT_INT DW WDT_INT DW AD_INT DW NOT_USED DW NOT_USED DW NOT_USED DW NOT_USED DW TMR1_INT DW TMR0_INT DW ...
Page 30
Data Memory Figure 8-7 shows the internal Data Memory space availa- ble. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. 0000H USER MEMORY (including STACK) 007FH 0080H 00BFH 00C0H CONTROL REGISTERS 00FFH ...
Page 31
HMS87C130XA/120XA/110XA Note: Several names are given at same address. Refer to below table. When read Addr. Timer Capture PWM Mode Mode Mode D1H T0 CDR0 D3H - D4H T1 CDR1 T1PDR ECH BITR Table 8-2 Various Register Name in Same ...
Page 32
Address Name Bit 7 C0H RA RA Port Data Register C1H RAIO RA Port Direction Register C2H RB RB Port Data Register C3H RBIO RB Port Direction Register C4H RC RC Port Data Register C5H RCIO RC Port Direction Register ...
Page 33
HMS87C130XA/120XA/110XA 8.4 Addressing Mode The HMS87C1X0XA uses six addressing modes; • Register addressing • Immediate addressing • Direct page addressing • Absolute addressing • Indexed addressing • Register-indirect addressing (1) Register Addressing Register addressing accesses the ...
Page 34
The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 983500 INC !0035H 0035 data 0F100 0F101 H address: 0035 0F102 00 H ...
Page 35
HMS87C130XA/120XA/110XA Y indexed direct page (8 bit offset) This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead ...
Page 36
Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10 H 1725 ADC ...
Page 37
HMS87C130XA/120XA/110XA 9. I/O PORTS The HMS87C1X0XA has four ports, RA, RB, RC and RD. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In gen- eral, when a initial reset state, all ...
Page 38
RB and RBIO registers 5-bit bidirectional I/O port (address C2 can be set individually as input and output through the RBIO register (address addition, Port RB is mul- H tiplexed with various special ...
Page 39
HMS87C130XA/120XA/110XA 9.3 RC and RCIO registers 2-bit bidirectional I/O port (address C4 pin can be set individually as input and output through the RC Data Register - - - RC 36 PORT RBFUNC.4~0 0 RB4 (Normal I/O ...
Page 40
RD and RDIO registers 4-bit bidirectional I/O port (address C6 pin can be set individually as input and output through the RDIO register (address Data Register ADDRESS : C6H RD RESET VALUE ...
Page 41
HMS87C130XA/120XA/110XA 10. CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and pe- ripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic ...
Page 42
EXT the operating temperature. The user needs to take into account variation due to toler- ance of external R and C components used. ...
Page 43
HMS87C130XA/120XA/110XA 11. BASIC INTERVAL TIMER The HMS87C1X0XA has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 11-1.The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is ...
Page 44
TIMER / COUNTER The HMS87C1X0XA has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either two 8-bit Timer/ Counter or ...
Page 45
HMS87C130XA/120XA/110XA 16BIT CAP0 CAP1 PWME The value “0” or “1” corresponding your operation. ...
Page 46
These timers have each 8-bit count register and data regis- ter. The count register is increased by every internal or ex- ternal clock input. The internal clock has a prescaler divide ratio option 32,128, 512, 2048 ...
Page 47
HMS87C130XA/120XA/110XA 12.2 16-bit Timer/Counter Mode The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000 matches TDR0, TDR1 and then resets to 0000 match output generates Timer 0 interrupt not ...
Page 48
This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 12-8, the pulse width of captured signal is wider than the ...
Page 49
HMS87C130XA/120XA/110XA T0 Ext. INT0 Pin Interrupt Request (INT0F) Ext. INT0 Pin Interrupt Request (INT0F) Ext. INT0 Pin Interrupt Request (INT0F) Interrupt Request (T0F n Interrupt Interval Period Clear ...
Page 50
Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit ...
Page 51
HMS87C130XA/120XA/110XA If it needed more higher frequency of PWM, it should be reduced resolution. Frequency Resolution T1CK[1:0] = T1CK[1:0] = 00(125nS) 01(250nS) 10-bit 7.8KHz 3.9KHz 9-bit 15.6KHz 7.8KHz 8-bit 31.2KHz 15.6KHz 7-bit 62.5KHz 31.2KHz Table 12-2 PWM Frequency vs. Resolution ...
Page 52
XIN PWM POL=1 PWM POL=0 Duty Cycle [80H x 125nS = 16uS] Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz] T1CK[1: XIN PWM0HR = 0CH T1PPR = FFH T1PDR = ...
Page 53
HMS87C130XA/120XA/110XA 13. BUZZER OUTPUT FUNCTION The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz MHz) by user ...
Page 54
ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of ...
Page 55
HMS87C130XA/120XA/110XA A/D Control Register - - ADCM Reserved A/D Result Data Register ADCR7 ADCR6 ADCR ENABLE A/D CONVERTER A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT A/D START (ADST = 1) NOP ADSF = 1 YES READ ADCR Figure 14-3 A/D ...
Page 56
Pins AN0/RB0 and AN1/RA1 to AN7/RA7 The analog input pins AN0 to AN7 also function as input/ output port (PORT RA and RB0) pins. When A/D conver- sion is performed with any of pins AN0 to AN7 selected, be ...
Page 57
HMS87C130XA/120XA/110XA 15. INTERRUPTS The HMS87C1X0XA interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag(“I” flag of PSW). The configuration of interrupt circuit is ...
Page 58
The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are ...
Page 59
HMS87C130XA/120XA/110XA 15.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” reset or an in- struction. Interrupt acceptance sequence requires =4MHz) after ...
Page 60
The following method is used to save/restore the general- purpose registers. Example: Register save using push and pop instructions INTxx: PUSH A ;SAVE ACC. PUSH X ;SAVE X REG. PUSH Y ;SAVE Y REG. interrupt processing POP Y ;RESTORE Y ...
Page 61
HMS87C130XA/120XA/110XA 15.2 External Interrupt The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6 ) as shown in Figure 15-6. H The edge detection of external interrupt has three transition ...
Page 62
WATCHDOG TIMER The purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. The watchdog timer has two types ...
Page 63
HMS87C130XA/120XA/110XA 17. POWER SAVING MODE For applications where power consumption is a critical factor, device provides three kinds of power saving func- tions, STOP mode, Wake-up Timer mode and internal RC- oscillated watchdog timer mode. The power saving function is ...
Page 64
than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. ...
Page 65
HMS87C130XA/120XA/110XA Oscillator (X pin) IN Internal Clock RESET Internal RESET 17.2 Wake-up Timer Mode In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler (only 2048 divided ratio) and Timer0, all functions are stopped, but the ...
Page 66
Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out ...
Page 67
HMS87C130XA/120XA/110XA Oscillator (X pin) IN Internal RC Clock Internal Clock RESET RESET by WDT Internal RESET Figure 17-6 Internal RCWDT Mode Releasing by RESET 17.4 Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current ...
Page 68
INPUT PIN internal pull- GND X Weak pull-up current flows Figure 17-7 Application Example of Unused Input Port OUTPUT PIN ON OFF i GND X In the left case, much current flows from port to GND. Figure ...
Page 69
HMS87C130XA/120XA/110XA 18. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, ...
Page 70
The time between when the Basic interval timer senses a high on the RESET pin, and when the RESET pin (and V ) actually reach their full value, is too long. In this sit- DD uation, when the Basic interval ...
Page 71
HMS87C130XA/120XA/110XA 19. POWER FAIL PROCESSOR The HMS87C1X0XA has an on-chip power fail detection circuitry to immunize against power noise. A Power Fail Detector Register, PFDR can enable (if clear/pro- grammed) or disable (if set) the Power fail Detect circuitry. If ...
Page 72
V DD Internal RESET V DD When PFDM = 1 Internal RESET V DD Internal RESET V DD System Clock When PFDM = System Clock Apr. 2001 ver1.0 RESET VECTOR PFS =1 NO RAM CLEAR INITIALIZE RAM ...
Page 73
HMS87C130XA/120XA/110XA 20. OTP PROGRAMMING The HMS87C130XA is one-time PROM(OTP) microcon- troller with 4K/2K bytes electrically programmable read only memory. 20.1 DEVICE CONFIGURATION AREA The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as secu- ...
Page 74
V User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RD0 7 RD1 8 RBB0/AN0/AVref 9~14 RB1~4, RD2 OUT 17 RESET 18 ...
Page 75
HMS87C130XA/120XA/110XA V User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RB0/AN0/AVref 7 RB1/BUZ 8 RB2/INT0 9,10 RB3 OUT 13 RESET 14 ...
Page 76
User Mode Pin No. Pin Name 1 RA4 (AN4) 2 RA5 (AN5) 3 RA6 (AN6) 4 RA7 (AN7 RB0/AN0/AVref 7 RB2/INT0 8 RB4/PWM/COMP OUT 11 RESET RA0 ...
Page 77
HMS87C130XA/120XA/110XA T SET1 EPROM Enable T VPPS VDDS CTL0 0V 0V CTL1 CTL2 0V A_D7~ A_D0 V DD1H V DD Figure 20-5 Timing Diagram in Program (Write & Verify) Mode T SET1 EPROM Enable T VPPS ...
Page 78
Parameter Programming Supply Current Supply Current in EPROM Mode V Level during Programming PP V Level in Program Mode DD V Level in Read Mode DD CTL2~0 High Level in EPROM Mode CTL2~0 Low Level in EPROM Mode A_D7~A_D0 High ...
Page 79
HMS87C130XA/120XA/110XA START Set Set Verify blank First Address Location Next address location N=1 EPROM Write 100uS program time Verify pass Apply 3N program cycle NO Last address 76 DD1H Report IHP Programming failure NO ...
Page 80
Apr. 2001 ver1.0 START Set V =V DD2H DD Set V =V IHP PP First Address Location Next address location NO Last address YES Report Read =0V PP END Figure 20-8 Reading Flow Chart HMS87C130XA/120XA/110XA ...
Page 81
APPENDIX ...
Page 82
APPENDIX A. INSTRUCTION MAP 00000 00001 00010 00011 LOW HIGH SET1 BBS BBS 000 - dp.bit A.bit,rel dp.bit,rel 001 CLRC 010 CLRG 011 DI 100 CLRV 101 SETC 110 SETG 111 EI 10000 10001 10010 10011 ...
Page 83
HMS87C130XA/120XA/110XA B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC 1 ADC #imm 2 ADC dp 3 ADC ADC !abs 5 ADC !abs + Y 6 ADC [ ADC [ dp ...
Page 84
NO. MNEMONIC 45 EOR #imm 46 EOR dp 47 EOR EOR !abs 49 EOR !abs + Y 50 EOR [ EOR [ EOR { X } ...
Page 85
HMS87C130XA/120XA/110XA 2. REGISTER / MEMORY OPERATION NO. MNEMONIC 1 LDA #imm 2 LDA dp 3 LDA LDA !abs 5 LDA !abs + Y 6 LDA [ LDA [ ...
Page 86
OPERATION NO. MNEMONIC 1 ADDW dp 2 CMPW dp 3 DECW dp 4 INCW dp 5 LDYA dp 6 STYA dp 7 SUBW dp 4. BIT MANIPULATION NO. MNEMONIC 1 AND1 M.bit 2 AND1B M.bit 3 BIT dp ...
Page 87
HMS87C130XA/120XA/110XA 5. BRANCH / JUMP OPERATION NO. MNEMONIC 1 BBC A.bit,rel 2 BBC dp.bit,rel 3 BBS A.bit,rel 4 BBS dp.bit,rel 5 BCC rel 6 BCS rel 7 BEQ rel 8 BMI rel 9 BNE rel 10 BPL rel 11 BRA ...
Page 88
CONTROL OPERATION & etc. NO. MNEMONIC 1 BRK NOP 5 POP A 6 POP X 7 POP Y 8 POP PSW 9 PUSH A 10 PUSH X 11 PUSH Y 12 PUSH PSW 13 ...