HY5DU283222Q-5 Hynix Semiconductor, HY5DU283222Q-5 Datasheet
HY5DU283222Q-5
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HY5DU283222Q-5 Summary of contents
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... GDDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Oct. 02 HY5DU283222Q HY5DU283222Q 1 ...
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... Input leakage current changed from +/-5uA to +/-2uA 1.1 1) Added 200MHz with CL3 at 250/222MHz speed bin 1.2 2) 200MHz IDD4 SPEC changed from 300mA to 370mA Rev. 1.2/Oct. 02 History HY5DU283222Q Date Remark Jun. 2001 Aug. 2001 Oct. 2001 Oct. 2001 Nov. 2001 Dec. 2001 May ...
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... ORDERING INFORMATION Part No. Power Supply HY5DU283222Q-4 HY5DU283222Q-45 V DD/ = 2.5V HY5DU283222Q-5 HY5DU283222Q-55 Rev. 1.2/Oct. 02 • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Write mask byte controls by DM (DM0 ~ DM3) • ...
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... DQ23 21 VDDQ 22 DM0 23 DM2 24 /WE 25 /CAS 26 /RAS 27 /CS 28 BA0 29 BA1 30 Auto Precharge Flag Rev. 1.2/Oct. 02 TOP VIEW 20mm x 14mm 100 Pin QFP 0.65mm Pitch ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh HY5DU283222Q 4Mx32 4banks ...
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... Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU283222Q 5 ...
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... Rev. 1.2/Oct. 02 Write Data Register 2-bit Prefetch Unit 64 Bank 1Mx32/Bank0 Control 1Mx32 /Bank1 1Mx32 /Bank2 1Mx32 /Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU283222Q DQ[0:31] DQS Data Strobe Transmitter Data Strobe DS Receiver 6 ...
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... If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 1.2/Oct. 02 CKEn CS RAS HY5DU283222Q A8/ CAS WE ADDR code code Note 1 1,4 X ...
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... Write Mask command masks burst write data with reference to DQS(Data Strobes) and it is not related with read data. 2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the data on DQ24-Q31. Rev. 1.2/Oct. 02 /CS, /RAS, CKEn /CAS, / HY5DU283222Q A8/ DM(0~3) BA ADDR Note ...
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... BA OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU283222Q Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set DSEL NOP NOP NOP BST ILLEGAL ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222Q Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL ...
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... L BA OPCODE BA, CA, AP READ/READAP HY5DU283222Q Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter ROW ACT after tWR NOP ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU283222Q Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ...
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... HY5DU283222Q /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle X Exit power down, enter idle X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue power down mode ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU283222Q SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... V in the following power up sequencing and attempt to maintain CKE at LVC- REF supply into any pin. Sequencing Voltage relationship to avoid latch-up After or with V DD After or with V DDQ After or with V DDQ HY5DU283222Q , then and finally DDQ . Except for TT < 0.3V DD < 0.3V DDQ < ...
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... CODE CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU283222Q AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... CAS Latency BT A7 Test Mode 0 Normal Vendor 1 test mode A8 DLL Reset Yes CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved HY5DU283222Q Burst Length Burst Length Sequential Reserved Reserved Reserved Reserved Reserved A3 Burst Type 0 Sequential 1 Interleave Interleave Reserved Reserved Reserved Reserved Reserved ...
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... A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 1.2/Oct. 02 Sequential XX0 0, 1 XX1 1, 0 X00 X01 X10 X11 000 001 010 011 100 101 110 111 HY5DU283222Q Interleave ...
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... OUTPUT DRIVER IMPEDANCE CONTROL The HY5DU283222Q supports both Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength ...
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... RFU* BA0 MRS Type 0 MRS 1 EMRS * All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 1.2/Oct RFU HY5DU283222Q DLL A0 DLL enable 0 Enable 1 Diable Output Driver Impedance Control RFU* Half RFU* Matched Impedance (Weak) 20 ...
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... SS Max Unit 2.5 2.625 V 2.5 2.625 0.3 V DDQ - V - 0.15 V REF V + 0.04 V REF REF 0.51*V V DDQ DDQ = 0V) SS Max Unit 0. disabled 2.7V OUT OUT HY5DU283222Q Unit ⋅ sec Note Note -15.2mA +15.2mA OL 21 ...
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... IL CK CKE ≥ V (min), /CS ≥ V (min min, Input signals are changed CK one time during 2clks t ≥ t (min), I =0mA All banks active t ≥ t (min), RC RFC All banks active CKE ≤ 0.2V HY5DU283222Q = 0V) SS Speed Unit 260 250 240 230 130 110 ...
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... 0.45 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DU283222Q = 0V) SS Max Unit 0.45 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 ...
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... DAL 0.45 0.55 0.45 0. 0.45 0.55 0.45 0. -0.9 0.9 -0 -0.7 0.7 -0.7 DQSCK t - 0.4 - DQSQ t t HPmin HPmin QHS QHS t t CH/L CH min min t - 0.6 - QHS t 1 1.0 - 1.0 IH HY5DU283222Q 5 55 Min Max Min Max 120K 38.5 120K ...
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... RPST WPRES t 1.5 - 1.5 WPREH t 0.4 0.6 0.4 WPST MRD t 200 - 200 XSC t - 7.8 - REFI HY5DU283222Q 5 55 Min Max Min Max 0.6 0.4 0.6 0.4 0.6 0.6 0.4 0.6 0.4 0.6 0.75 1.25 0.75 1.25 - 0. 0.45 - 0.45 - 1.1 0.8 1 ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output Rev. 1.2/Oct. 02 Pin CK, /CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ =50Ω T Zo=50Ω V REF C =30pF L HY5DU283222Q Symbol Min Max Unit C 1.7 2 1.7 2 3.7 4 ...
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... Low Quad Flat Package 22.10(0.870) 21.90(0.862) 20.10(0.791) 19.90(0.783) 1.60(0.063) 1.45(0.057) All dimension in mm (inches). Notation is Rev. 1.2/Oct. 02 Unit:mm(inch) Base Plane Seating Plane MAX or typical. MIN HY5DU283222Q Detail A Gauge Line 0.15(0.006) 0.20(0.008) 0.05(0.002) 0.09(0.004) 0~7 Deg 0.75(0.029) 0.50(0.020) 0.66(0.026) 0.45(0.018) 1.00(0.0394)REF 27 ...