DS2151Q Dallas Semiconductor, DS2151Q Datasheet
DS2151Q
Specifications of DS2151Q
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DS2151Q Summary of contents
Page 1
... Industrial grade version (- +85 C) available (DS2151QN) DESCRIPTION The DS2151Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection to T1 lines whether they be DS-1 long haul or DSX-1 short haul. automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line build outs as well as CSU build outs of -7 ...
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... The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing pattern ...
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... DS2151Q BLOCK DIAGRAM Figure 1 DS2151Q ...
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... T1 channels. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional T1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications. See Section 13 for timing details DS2151Q ...
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... TSYNC I/O Transmit Sync. multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames. See Section 13 for timing details ...
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... TCLK I 39 TSER I 40 TCHCLK O 41 AD0 I/O 42 AD1 43 AD2 44 AD3 DS2151Q REGISTER MAP ADDRESS R/W REGISTER NAME 20 R/W Status Register 1. 21 R/W Status Register 2. 22 R/W Receive Information Register Line code Violation Count Register Line code Violation Count Register 2. 25 ...
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... All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics for more details. The multiplexed bus on the DS2151Q saves pins because the address information and data information share the same signal paths. The addresses are presented to the pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus cycle ...
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... DS2151Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or data during the latter portion of the high impedance state as RD The DS2151Q can also be easily connected to non-multiplexed buses. Please see the separate Application Note for a detailed discussion of this topic ...
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... Fs bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select. 0=count errors in the framing bit position 1=count the number of multiframes out of sync TCPT RBSE GB7S DS2151Q (LSB) RD4YM FSBE MOSCRF (LSB) TLINK TBL TYEL ...
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... TYEL TCR1.0 Note: for a detailed description of how the bits in TCR1 affect the transmit side formatter of the DS2151Q, please see Figure 13-9. Loss Of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present RCLK if the TCLK input should fail to transition (see Figure 1- 1 for more details) ...
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... I/O pins and parallel port pins) force all output pins low (including all I/O pins except parallel port pins) force all output pins high (including all I/O pins except parallel port pins DS2151Q (LSB) TSIO TD4YM ...
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... CCR1.0 LOCAL LOOPBACK When CCR1.6 is set the DS2151Q will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator and the jitter attenuator should be programmed the transmit path ...
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... BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2151Q as it would normally and the data at the TSER input will be ignored. Data in this loopback will pass through the jitter attenuator. RLB is used to place the DS2151Q into “ ...
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... Receive Frame Mode Select. 0=D4 framing mode 1=ESF framing mode Receive B8ZS Enable. 0=B8ZS disabled 1=B8ZS enabled Receive SLC-96 Enable. 0=SLC-96 disabled 1=SLC-96 enabled Receive FDL 0 Destuffer Enable. 0=0 destuffer disabled 1=0 destuffer enabled DS2151Q (LSB) RB8ZS RSLC96 RFDL ...
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... CCR3.0 LOOP CODE GENERATION When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted payload with either the Loop Up or Loop Down code respectively. repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as long as either bit is set ...
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... The user will always precede a read of these registers with a write. The byte written to the register will inform the DS2151Q which bits the user wishes to read and have cleared. The user will write a byte to one of these four registers, with the bit positions he or she wishes to read and the bit positions he or she does not wish to obtain the latest information on ...
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... B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.6. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error DS2151Q (LSB) SEFE B8ZS FBE Set when the last resync ...
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... RL1 RIR2.7 RL0 RIR2.6 TESF RIR2.5 TESE RIR2.4 TSLIP RIR2.3 JALT RIR2.2 RPDV RIR2.1 TPDV RIR2.0 DS2151Q RECEIVE T1 LEVEL INDICATION Table 4-1 RL1 RL0 TESF TESE TSLIP Receive Level Bit 1. See Table 4-1. Receive Level Bit 0. See Table 4-1. Transmit Elastic Store Full. Set when the transmit elastic store buffer fills and a frame is deleted ...
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... RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 RCL SR1.1 RLOS SR1.0 DS2151Q ALARM SET AND CLEAR CRITERIA Table 4-2 ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm 1. D4 bit 2 mode (RCR2.2= F-bit mode (RCR2.2=1; this mode is also referred to as the “Japanese Yellow Alarm” ...
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... After this initial indication recommended that the software poll the DS2151Q every 100 ms to 500 ms until 5 seconds have elapsed to insure that the code is continuously present. Once 5 seconds have passed, the DS2151Q should be taken into or out of loopback via the Remote Loopback (RLB) bit in CCR1 ...
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... Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Blue Alarm. 0=interrupt masked 1=interrupt enabled Receive Yellow Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled DS2151Q (LSB) RYEL RCL RLOS ...
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... ERROR COUNT REGISTERS There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the CRC6 code words, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters are automatically updated on one second boundaries as determined by the one second timer in Status Register 2 (SR2 ...
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... CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, the DS2151Q can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOS=1) conditions. ...
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... LSB of the 12-Bit Multiframes Out of Sync or F-Bit Error Count (note 2) MOS number of multiframes out of sync F-Bit errors in the Ft pattern MOS number of multiframes out of sync F-Bit errors in the FPS pattern WHAT IS COUNTED IN THE PCVCRs (LSB) (note 1) (note 1) (note 1) MOS/FB1 MOS/FB0 WHAT IS COUNTED IN THE MOSCRs DS2151Q MOSCR1 MOSCR2 ...
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... If the 0 destuffer sees six or more row followed the 0 is not removed. The CCR2.0 bit should always be set when the DS2151Q is extracting the FDL. More on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate Application Note. ...
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... If it finds such a pattern, it will automatically insert a 0 after the five 1s. The CCR2.4 bit should always be set when the DS2151Q is inserting the FDL. More on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate Application Note. ...
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... The Robbed-Bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2151Q. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. ...
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... DS2151Q will load the values in the TSRs into the outgoing shift register every other D4 multiframe. 8.0 SPECIAL TRANSMIT SIDE REGISTERS There is a set of seven registers in the DS2151Q that can be used to custom tailor the data that transmitted onto the T1 line channel by channel basis. Each of the 24 T1 channels can be either forced to be transparent or to have a user defined idle code inserted into them ...
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... Idle Code into this DS0 channel TIR1.0 1=insert the Idle Code into this channel TIDR4 TIDR3 TIDR.7 MSB of the Idle Code TIDR.0 LSB of the Idle Code DS2151Q (LSB) CH2 CH1 TTR1 (39) CH10 CH9 TTR2 (3A) CH18 CH17 TTR3 (3B) ...
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... CH24 CH1 10.0 ELASTIC STORES OPERATION The DS2151Q has two onboard two-frame (386 bits) elastic stores. These elastic stores have two main purposes. First, they can be used to rate-convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps), which is the E1 rate. Secondly, they can be used to absorb the differences in frequency and phase between the T1 data stream and an asynchronous (i ...
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... RCLK and all of the slip contention logic in the DS2151Q is disabled (since slips cannot occur). Also, since the buffer depth is no longer two frames deep, the DS2151Q must be set up to source either a frame or multiframe pulse at the RSYNC pin. On power-up after the SYSCLK has locked to the RCLK signal, the Elastic Store Reset bit (CCR3 ...
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... CH1 12.0 LINE INTERFACE FUNCTIONS The line interface function in the DS2151Q contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below ...
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... EGL bit should be set some applications, more sensitivity than -30 dB may be required and the DS2151Q will allow the receiver low as - the EGL bit is set to 0. However, when the EGL bit is set to 0, the DS2151Q will be more susceptible to crosstalk and its jitter tolerance will suffer. ...
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... DC Resistance 12.3 JITTER ATTENUATOR The DS2151Q contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. ...
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... PARAMETER Parallel Resonant Frequency Mode Load Capacitance Tolerance Pullability Effective Series Resistance Crystal Cut DS2151Q EXTERNAL ANALOG CONNECTIONS Figure 12-1 NOTE: See the separate Application Note for details on how to construct a protected interface. SPECIFICATION 6.176 MHz Fundamental (18.5 pF nominal) 50 ppm CL=10 pF, delta frequency=+175 to +250 ppm ...
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... DS2151Q JITTER TOLERANCE Figure 12-2 DS2151Q TRANSMIT WAVEFORM TEMPLATE Figure 12 DS2151Q ...
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... DS2151Q JITTER ATTENUATION Figure 12-4 13.0 TIMING DIAGRAMS RECEIVE SIDE D4 TIMING Figure 13-1 NOTES: 1. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0). 2. RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1). 3. RSYNC in the multiframe mode (RCR2.4=1). ...
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... RSYNC in the multiframe mode (RCR2.4=1). 4. ZBTSI mode disabled (RCR2.6=0). 5. RLINK data (FDL bits) is updated 1 bit-time before odd frames and held for two frames. 6. ZBTSI mode is enabled (RCR2.6=1). 7. RLINK data (Z bits) is updated 1 bit-time before odd frame and held for four frames DS2151Q ...
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... RECEIVE SIDE BOUNDARY TIMING WITH ELASTIC STORE(S) DISABLED Figure 13-3 NOTES: 1. RCHBLK is programmed to block channel 24 ESF boundary is shown. 1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13-4 NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RCHBLK is programmed to block channel 24 DS2151Q ...
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... TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0). 2. TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1). 3. TSYNC in the multiframe mode (TCR2.3=1). 4. TLINK data (S-bit) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1. DS2151Q ...
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... TLINK data (FDL bits) is sampled during the F-bit time of odd frame and inserted into the outgoing T1 stream if enabled via TCR1.2. 6. ZBTSI mode is enabled (TCR2.5=1). 7. TLINK data (Z bits) is sampled during the F-bit time of frame 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1. DS2151Q ...
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... TRANSMIT SIDE BOUNDARY TIMING (WITH ELASTIC STORE(S) DISABLED) Figure 13-8 NOTES: 1. TSYNC is in the input mode (TCR2.2=0). 2. TSYNC is in the output mode (TCR2.2=1). 3. TCHBLK is programmed to block channel 1. 4. See Figures 13-4 and 13-5 for details on timing with the transmit side elastic store enabled DS2151Q ...
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... DS2151Q TRANSMIT DATA FLOW Figure 13 DS2151Q ...
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... Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) NOTES: 1. Applies to RVDD, TVDD, and DVDD. 2. TCLK=1.544 MHz. 3. 0.0V < V < Applies to and INT1 INT1 -1.0V to +7. (- +85 C for DS2151QN) - +125 C 260°C for 10 seconds SYMBOL MIN 4.75 DD SYMBOL MIN C IN ...
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... ALE fall Muxed Address Hold Time Delay Time DS ALE Rise Pulse Width AS or ALE High Delay Time ALE to DS Output Data Delay Time from Data Setup Time INTEL BUS READ AC TIMING (- +85 C for DS2151QN) SYMBOL MIN TYP t 250 CYC PW 150 EL PW 100 ...
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... INTEL BUS WRITE AC TIMING MOTOROLA BUS AC TIMING DS2151Q ...
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... Jitter attenuator enabled in the receive side path. 2. Jitter attenuator disabled or enabled in the transmit path. 3. SYSCLK=1.544 MHz 4. SYSCLK=2.048 MHz SYMBOL MIN TYP t 648 CP t 230 324 CH t 230 324 CL t 115 CH t 115 CL t 648 SP t 488 (- +85 C for DS2151QN) MAX UNITS 110 ns DS2151Q 5%) NOTES ...
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... RECEIVE SIDE AC TIMING NOTES: 1. RSYNC is in the output mode (RCR2.3=0). 2. RSYNC is in the input mode (RCR2.3=1). 3. RLCLK and RLINK only have a timing relationship to RCLK. 4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path DS2151Q ...
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... Delay TCLK to TCHCLK Delay TCLK to TCHBLK Delay TCLK to TSYNC Delay TCLK to TLCLK NOTE: If the transmit side elastic store is enabled, then TSER is sampled on the falling edge of SYSCLK and the parameters t and t still apply SYMBOL MIN TYP t 648 (- +85 C for DS2151QN) MAX UNITS DS2151Q 5%) NOTES 1 1 ...
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... TRANSMIT SIDE AC TIMING NOTES: 1. TSYNC is in the output mode (TCR2.2=1). 2. TSYNC is in the input mode (TCR2.2=0). 3. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled DS2151Q ...
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... DS2151Q T1 CONTROLLER 44-PIN PLCC DS2151Q ...