M69AR048BL70ZB8 STMicroelectronics, M69AR048BL70ZB8 Datasheet
M69AR048BL70ZB8
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M69AR048BL70ZB8 Summary of contents
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FEATURES SUMMARY SUPPLY VOLTAGE: 1.65 to 1.95V ACCESS TIMES: 70ns, 80ns, 85ns LOW STANDBY CURRENT: 100µA DEEP POWER-DOWN CURRENT: 10µA BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O 8 WORD PAGE ACCESS CAPABILITY: 25ns WIDE ...
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M69AR048B Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 25.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The M69AR048B Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 1.65V to 1.95V supply voltage range. M69AR048B is a member of STMicroelectronics 1T/1C (one transistor per cell) memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area ...
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Figure 3. TFBGA Connections (Top view through package DQ8 DQ9 A5 A6 DQ10 V SS DQ11 A17 ...
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M69AR048B SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access ...
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Figure 4. Block Diagram INTERNAL GENERATOR ADDRESS CONTROL CONTROLLER V SS ARBITRATION LOGIC CLOCK REFRESH CONTROLLER DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER COLUMN DECODER LOGIC ADDRESS POWER M69AR048B DQ0-DQ7 DQ8-DQ15 AI07221 7/29 ...
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M69AR048B OPERATION Operational modes are determined by device con- trol inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2). Power Up Sequence Because the internal control logic of the M69AR048B needs to ...
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The data of the fourth cycle must be all 0s, and the data of the fifth cycle is the Power-Down Configuration data (see 5., Power-Down Configuration cycle is written into a different address, the se- quence ...
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M69AR048B Table 4. Power-Down Program Sequence Cycle # Operation 1st 2nd 3rd 4th 5th 6th Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Mode Deep Power-Down (default) 4Mb Partial Power-Down 8Mb Partial Power-Down 16Mb Partial Power-Down Table 6. ...
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... Storage Temperature STG V Core Supply Voltage CC V Input or Output Voltage IO these or any other conditions above those indicat the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter M69AR048B Min Max Unit – – ...
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M69AR048B DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under ...
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Figure 7. AC Measurement I/O Waveform I/O Timing Reference Voltage Output Transition Timing Reference Voltages Table 10. DC Characteristics Symbol Parameter I CC1 V Active Current CC I CC2 I V Page Read Current ...
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M69AR048B Table 11. Read Mode AC Characteristics Symbol Alt. (1,2,9) t Address Valid Time t RC AVAX (1,5,6,9) t Page Read Cycle Time t PRC AVAX2 (1,5,6,9) t Page Read Cycle Time t PRC AVEH2 t t Address Valid to ...
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Figure 8. Address Controlled, Read Mode AC Waveforms A0-A20 tAVEL E1 G LB, UB DQ0-DQ15 Note High High. Figure 9. Address and Output Enable Controlled, Read Mode AC Waveforms tAXAV A0-A20 E1 G UB, LB DQ0-DQ15 ...
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M69AR048B Figure 10. UB/LB Controlled, Read Mode AC Waveforms tAXAV A0-A20 tAVQV E1 Low tBLQV LB UB tBLQX DQ0-DQ7 DQ8-DQ15 Note High Low High. Figure 11. Page Address and Chip Enable Controlled, Read Mode ...
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Figure 12. Random and Page Address Controlled, Read Mode AC Waveforms tAXAV A20-A3 tAVAX ADDRESS A2-A0 VALID tAVQV E Low tGLQV G tBLQV LB, UB tGLQX tBLQX DQ0-DQ15 Note High. tAVAX ADDRESS VALID tAXAV2 tAXAV tAVAX2 ADDRESS ADDRESS ...
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M69AR048B Table 12. Write Mode AC Characteristics Symbol Alt. (1,2) t Write Cycle Time t WC AVAX (2) t Address Valid to LB, UB Low t AS AVBL (2) t Address Valid to Chip Enable Low t AS AVEL (2) ...
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Figure 13. Chip Enable Controlled, Write AC Waveforms A0-A20 tAVEL E1 tAVWL W tAVBL LB, UB tGHEL G DQ0-DQ15 Note High. Figure 14. Write Enable Controlled, Write AC Waveforms A0-A20 E1 Low tAVWL W LB DQ0-DQ15 ...
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M69AR048B Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 1 A0-A20 E1 Low tAVWL DQ0-DQ7 DQ8-DQ15 Note High. Figure 16. Write Enable and UB/LB Controlled, Write AC Waveforms 2 A0-A20 E1 Low W ...
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Figure 17. Write Enable and UB/LB Controlled, Write AC Waveforms 3 A0-A20 E1 Low W tAVBL LB UB DQ0-DQ7 DQ8-DQ15 Note High. Figure 18. Write Enable and UB/LB Controlled, Write AC Waveforms 4 A0-A20 E1 Low W tAVBL ...
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M69AR048B Figure 19. Chip Enable Controlled, Read and Write Mode AC Waveforms A0-A20 tEHAX E1 tEHEL W UB, LB tGHEL G tEHQZ tEHQX READ DATA DQ0-DQ15 OUTPUT Note: Write address is valid from either last falling ...
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Figure 21. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms tAXAV A0-A20 E1 Low tAVWL W UB tGHQZ tGHQX DATA DQ0-DQ15 OUT Note: E1 can be tied to Low for W and G controlled ...
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M69AR048B Table 13. Standby Mode AC Characteristics Symbol Alt Low Setup Time for Power-Down Entry CLEX CSP Low Hold Time after Power-Down Entry EXCH C2LP E1 High Hold Time following E2 High after Power-Down ...
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Figure 24. Power-Down Mode AC Waveforms E1 E2 tCLEX DQ0-DQ15 Figure 25. Power-Up Mode AC Waveforms E1 E2 VCC Figure 26. Standby Mode Entry AC Waveforms, After Read E1 tEHGL G W Read Active Note High. tEXCH Power-Down ...
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M69AR048B PACKAGE MECHANICAL Figure 27. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View FE BALL "A1" Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, ...
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PART NUMBERING Table 15. Ordering Information Scheme Example: Device Type M69 = 1T/1C Memory Cell Architecture Mode A = Asynchronous Operating Voltage R = 1.65V to 1.95V Array Organization 048 = 32 Mbit (2Mb x16) Option ...
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... Configuration Data” and “Power- Down Configuration Address”. “Sleep” replaced by “Deep Power-down”. section corrected. All drawings converted to STMicroelectronics standard. For conformity with Figure 13., Chip Enable Controlled, Write AC changed to t Characteristics ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...