ST24E64 STMicroelectronics, ST24E64 Datasheet
ST24E64
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ST24E64 Summary of contents
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... SUPPORTS 400kHz PROTOCOL 1 MILLION ERASE/WRITE CYCLES, OVER the FULL SUPPLY VOLTAGE RANGE 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE – 4.5V to 5.5V for ST24E64 version – 2.5V to 5.5V for ST25E64 version WRITE CONTROL FEATURE BYTE and PAGE WRITE ( BYTES) BYTE, RANDOM and SEQUENTIAL READ ...
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... ST24E64, ST25E64 Figure 2A. DIP Pin Connections ST24E64 ST25E64 SCL SDA AI01205B Table 2. Absolute Maximum Ratings Symbol T Ambient Operating Temperature A T Storage Temperature STG T Lead Temperature, Soldering LEAD V Input or Output Voltages IO V Supply Voltage CC Electrostatic Discharge Voltage (Human Body model) V ESD Electrostatic Discharge Voltage (Machine model) Notes: 1. Except for the rating ” ...
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... V (see Table 5). IL When WC = ’1’, Device Select and Address bytes are acknowledged; Data bytes are not acknow- ledged. Refer to the AN404 Application Note for more de- tailed information about Write Control feature. ST24E64, ST25E64 establish the device and V ...
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... ST24E64, ST25E64 Figure 3. Maximum R Value versus Bus Capacitance ( BUS (pF) DEVICE OPERATION Bus Background The ST24/25E64 support the extended addressing protocol. This protocol defines any device that sends data onto the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave ...
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... Output Low Voltage (ST25 series) Test Condition 4.5V to 5.5V or 2.5V to 5.5V) CC Test Condition OUT CC SDA in Hi 400kHz C (Rise/Fall time < 30ns 5V 400kHz 2. 2.5V 400kHz 3mA 2.1mA 2. ST24E64, ST25E64 Min Max Unit 500 k 100 ns Min Max Unit 100 A 300 –0 –0.3 0 – 0 0.4 V 0.4 V 5/16 ...
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... ST24E64, ST25E64 Table 7. AC Characteristics (T = – Symbol Alt t t Clock Rise Time CH1CH2 Clock Fall Time CL1CL2 F ( SDA Rise Time DH1DH2 R ( SDA Fall Time DL1DL1 F ( Clock High to Input Transition CHDX SU:STA t t Clock Pulse Width High CHCL HIGH t t Input Low to Clock Low (START) ...
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... SDA IN tCHDX START CONDITION SCL tCLQV SDA OUT tDHDL SCL SDA IN tCHDH STOP CONDITION tCLCH tDXCX tCLDX SDA SDA INPUT CHANGE tCLQX DATA VALID DATA OUTPUT tW tCHDX WRITE CYCLE ST24E64, ST25E64 tCHDH tDHDL STOP & BUS FREE START CONDITION AI00795 7/16 ...
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... ST24E64, ST25E64 2 Figure Bus Protocol SCL SDA START CONDITION 1 SCL MSB SDA START CONDITION 1 2 SCL MSB SDA Write Operations Following a START condition the master sends a device select code with the RW bit reset to ’0’. The ST24/25E64 acknowledge this and waits for 2 bytes of address ...
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... Step1). WRITE Cycle in Progress with ACK Returned YES Next Operation is YES Addressing the Memory Send Byte Address Proceed WRITE Operation ST24E64, ST25E64 Proceed Random Address READ Operation AI01099B 9/16 ...
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... ST24E64, ST25E64 Figure 8. Write Modes Sequence with Write Control = 0 WC BYTE WRITE DEV SEL WC PAGE WRITE DEV SEL WC (cont’d) ACK PAGE WRITE DATA IN N (cont’d) Read Operations On delivery, the memory content is set at all ”1’s” (or FFh). Current Address Read. The ST24/25E64 have an internal 13 bits address counter ...
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... Acknowledge in Read Mode. In all read modes the ST24/25E64 wait for an acknowledge during the 9th bit time. If the master does not pull the SDA line low during this time, the ST24/25E64terminate the data transfer and switch to a standby state. ST24E64, ST25E64 NO ACK NO ACK DATA IN 2 AI01120 ...
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... ST24E64, ST25E64 Figure 10. Read Modes Sequence CURRENT ADDRESS DEV SEL READ RANDOM ADDRESS DEV SEL * READ SEQUENTIAL CURRENT DEV SEL READ SEQUENTIAL RANDOM DEV SEL * READ ACK DATA OUT N Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 4th byte) must be identical. ...
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... For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory Shortform catalogue. For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you. ST24E64 Package Temperature Range B PSDIP8 0.25mm Frame 6 – SO8 3 * –40 to 125 C 200mil Width ST24E64, ST25E64 Option TR Tape & Reel Packing 13/16 ...
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... ST24E64, ST25E64 PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame mm Symb Typ A 3.90 A1 0.49 A2 3.30 B 0.36 B1 1.15 C 0.20 D 9.20 E 7.62 E1 6.00 e1 2. 3.00 N PSDIP8 Drawing is not o scale 14/16 Min Max Typ 5.90 – 5.30 0.56 1.65 0.36 9.90 – – ...
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... Min Max Typ 2.03 0.25 1.78 0.45 – – 0.008 5.35 5.40 – – 0.050 8. ST24E64, ST25E64 inches Min Max 0.080 0.004 0.010 0.070 0.014 0.018 – – 0.203 0.211 0.205 0.213 – – 0.303 0.319 0.020 0.031 0.004 ...
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... ST24E64, ST25E64 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice ...