MC54HC4060J Motorola, MC54HC4060J Datasheet

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MC54HC4060J

Manufacturer Part Number
MC54HC4060J
Description
14-stage binary ripple counter with oscillator
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
14-Stage Binary Ripple
Counter with Oscillator
High–Performance Silicon–Gate CMOS
MC14060B. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
frequency that is controlled either by a crystal or by an RC circuit connected
externally. The output of each flip–flop feeds the next, and the frequency at
each output is half that of the preceding one. The state of the counter
advances on the negative–going edge of Osc In. The active–high Reset is
asynchronous and disables the oscillator to allow very low power consump-
tion during standby operation.
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may need to be gated with Osc Out 2 of the HC4060.
10/95
Motorola, Inc. 1995
The MC54/74HC4060 is identical in pinout to the standard CMOS
This device consists of 14 master–slave flip–flops and an oscillator with a
State changes of the Q outputs do not occur simultaneously because of
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 390 FETs or 97.5 Equivalent Gates
OSC IN
RESET
LOGIC DIAGRAM
OSC OUT 1
11
12
PIN 16 = V CC
PIN 8 = GND
10
OSC OUT 2
9
14
13
15
7
5
4
6
1
2
3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
1
REV 6
MC54/74HC4060
16
16
Clock
16
X
1
1
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDT
GND
ORDERING INFORMATION
Q12
Q13
Q14
1
Q6
Q5
Q7
Q4
FUNCTION TABLE
PIN ASSIGNMENT
Reset
H
L
L
1
2
3
4
5
6
7
8
Advance to Next State
CERAMIC PACKAGE
PLASTIC PACKAGE
All Outputs are Low
TSSOP PACKAGE
16
15
14
13
12
10
11
CASE 948F–01
9
Output State
CASE 620–10
CASE 648–08
DT SUFFIX
No Change
N SUFFIX
J SUFFIX
Ceramic
Plastic
TSSOP
V CC
Q10
Q8
Q9
RESET
OSC IN
OSC OUT 1
OSC OUT 2

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MC54HC4060J Summary of contents

Page 1

... Low Input Current High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 390 FETs or 97.5 Equivalent Gates LOGIC DIAGRAM OSC OUT 1 OSC OUT OSC IN 12 RESET PIN PIN 8 = GND 10/95 Motorola, Inc. 1995 Q10 1 Q12 ...

Page 2

... NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î ...

Page 3

... For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). * Osc In driven with external clock. ...

Page 5

... High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM PIN 4 Q10 = PIN PIN PIN PIN 14 GND = PIN PIN 13 For 2 OSC OUT The formula may vary for other frequen cies. 5 MC54/74HC4060 Q12 Q13 Q14 6 > > 400 Hz f 400 kHz Hz ohms farads MOTOROLA 3 ...

Page 6

... – load –jX Cs NOTE and out . considered as part of the load and R f typically have minimal effect below 2 MHz. Figure 8. Series Equivalent Crystal Load MOTOROLA 11 OSC IN 10 OSC OUT Figure 6. Pierce Crystal Oscillator Circuit Î Î Î Î Î Î Î Î ...

Page 7

... E. Hafner, “The Piezoelectric Crystal Unit – Definitions and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb. 1969. D. Kemper, L. Rosine, “Quartz Crystals for Frequency Control”, Electro–Technology, June, 1969 Ottowitz, “A Guide to Crystal Selection”, Electronic Design, May, 1966. 7 MC54/74HC4060 = 2, = 2/A where A is (1) (2) (3) MOTOROLA ...

Page 8

... MC54/74HC4060 OSC IN RESET Q10 Q11 Q12 Q13 Q14 MOTOROLA TIMING DIAGRAM 128 256 512 8 1024 2048 4096 8192 16,384 High–Speed CMOS Logic Data DL129 — Rev 6 ...

Page 9

... B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.070 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7. 0.020 0.040 0.51 1.01 MOTOROLA ...

Page 10

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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