MC54HC74AJ Motorola, MC54HC74AJ Datasheet

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MC54HC74AJ

Manufacturer Part Number
MC54HC74AJ
Description
Dual D flip-flop with set and reset
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D Flip-Flop with Set
and Reset
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Clock inputs. Information at a D–input is transferred to the corresponding Q
output on the next positive going edge of the clock input. Both Q and Q
outputs are available from each flip–flop. The Set and Reset inputs are
asynchronous.
10/95
Motorola, Inc. 1995
The MC54/74HC74A is identical in pinout to the LS74. The device inputs
This device consists of two D flip–flops with individual Set, Reset, and
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 128 FETs or 32 Equivalent Gates
RESET 1
CLOCK 1
CLOCK 2
RESET 2
DATA 1
DATA 2
SET 1
SET 2
LOGIC DIAGRAM
13
12
11
10
1
2
3
4
PIN 14 = V CC
PIN 7 = GND
5
6
9
8
Q1
Q2
Q2
Q1
3–1
REV 6
14
MC54/74HC74A
14
* Both outputs will remain high as long as
Set and Reset are low, but the output
states are unpredictable if Set and Reset
go high simultaneously.
Set Reset Clock Data
14
14
H
H
H
H
H
H
L
L
1
CLOCK 1
1
RESET 1
MC54HCXXAJ
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
DATA 1
ORDERING INFORMATION
1
SET 1
1
GND
H
H
H
H
H
H
L
L
Q1
Q1
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
1
2
3
4
5
6
7
H
X
X
X
L
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
SOIC PACKAGE
X
X
X
H
X
X
X
CASE 948G–01
L
CASE 751A–03
CASE 632–08
CASE 646–06
14
13
12
10
11
DT SUFFIX
9
8
N SUFFIX
D SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
TSSOP
No Change
No Change
No Change
V CC
RESET 2
DATA 2
CLOCK 2
SET 2
Q2
Q2
H*
Outputs
Q
H
H
L
L
H*
Q
H
H
L
L

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MC54HC74AJ Summary of contents

Page 1

... LOGIC DIAGRAM 1 RESET DATA CLOCK 1 4 SET 1 13 RESET DATA CLOCK 2 10 SET 2 PIN PIN 7 = GND 10/95 Motorola, Inc. 1995 3–1 REV 6 MC54/74HC74A J SUFFIX CERAMIC PACKAGE 14 CASE 632– SUFFIX PLASTIC PACKAGE CASE 646– SUFFIX 14 SOIC PACKAGE CASE 751A– SUFFIX ...

Page 2

... For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). Î Î Î Î Î Î Î Î ...

Page 3

... NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). ...

Page 4

... PLH t PHL 90% 50% 10 TLH t THL Figure 1. VALID 50% DATA 50% CLOCK Figure SET 2, 12 DATA 1, 13 RESET MOTOROLA SWITCHING WAVEFORMS 50% SET OR RESET GND t PHL 50 PLH 50 CLOCK V CC GND DEVICE UNDER V CC TEST GND * Includes all probe and jig capacitance EXPANDED LOGIC DIAGRAM ...

Page 5

... C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC 0.015 0.039 0.39 1.01 MOTOROLA ...

Page 6

... 14X REF 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 –V– C 0.10 (0.004) –T– SEATING G D PLANE MOTOROLA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE 0.25 (0.010 SUFFIX PLASTIC TSSOP PACKAGE CASE 948G–01 ISSUE ...

Page 7

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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