MC54HC393J Motorola, MC54HC393J Datasheet

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MC54HC393J

Manufacturer Part Number
MC54HC393J
Description
Dual 4-state binary ripple counter
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Stage
Binary Ripple Counter
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
parallel outputs from each counter stage. A
by cascading the two binary counters.
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393.
10/95
Motorola, Inc. 1995
The MC54/74HC393 is identical in pinout to the LS393. The device inputs
This device consists of two independent 4–bit binary ripple counters with
Internal flip–flops are triggered by high–to–low transitions of the clock
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 236 FETs or 59 Equivalent Gates
CLOCK
RESET
1, 13
2, 12
LOGIC DIAGRAM
PIN 14 = V CC
PIN 7 = GND
COUNTER
BINARY
3, 11
4, 10
256 counter can be obtained
5, 9
6, 8
Q1
Q2
Q3
Q4
1
REV 6
14
14
MC54/74HC393
14
CLOCK a
1
RESET a
Clock
1
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
H
X
L
ORDERING INFORMATION
1
GND
Q1 a
Q2 a
Q3 a
Q4 a
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
1
2
3
4
5
6
7
Reset
H
L
L
L
L
CERAMIC PACKAGE
PLASTIC PACKAGE
SOIC PACKAGE
CASE 751A–03
CASE 632–08
CASE 646–06
14
13
12
11
10
9
8
N SUFFIX
D SUFFIX
J SUFFIX
No Change
No Change
No Change
Advance to
Ceramic
Plastic
SOIC
Next State
Outputs
V CC
CLOCK b
RESET b
Q1 b
Q2 b
Q3 b
Q4 b
L

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MC54HC393J Summary of contents

Page 1

... High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 236 FETs or 59 Equivalent Gates LOGIC DIAGRAM 1, 13 BINARY CLOCK COUNTER 2, 12 RESET PIN PIN 7 = GND 10/95 Motorola, Inc. 1995 MC54/74HC393 14 256 counter can be obtained ...

Page 2

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î Î Î Î ...

Page 3

... NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 3. Test Circuit MOTOROLA PIN DESCRIPTIONS vided for each counter. A high at the Reset input prevents counting and forces all four outputs low. OUTPUTS Q1, Q2, Q3, Q4 (Pins 10, 11) Parallel binary outputs Q4 is the most significant bit. ...

Page 5

... CLOCK RESET Count Count High–Speed CMOS Logic Data DL129 — Rev 6 TIMING DIAGRAM COUNT SEQUENCE Outputs MC54/74HC393 MOTOROLA ...

Page 6

... SEATING PLANE –A– –B– SEATING PLANE 0.25 (0.010 MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC DIP PACKAGE CASE 632–08 ISSUE Y - 0.25 (0.010 SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F ...

Page 7

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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