MC54HC595AJ Motorola, MC54HC595AJ Datasheet

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MC54HC595AJ

Manufacturer Part Number
MC54HC595AJ
Description
8-bit serial-input/serial or parallel-output shift register
Manufacturer
Motorola
Datasheet
8-Bit Serial-Input/Serial or
Parallel-Output Shift Register
with Latched 3-State Outputs
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
CMOS MPUs and MCUs.
3/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
The MC54/74HC595A is identical in pinout to the LS595. The device
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
The HC595A directly interfaces with the Motorola SPI serial data port on
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
SERIAL
INPUT
DATA
OUTPUT
ENABLE
CLOCK
CLOCK
RESET
LATCH
SHIFT
A
14
10
12
13
11
REGISTER
SHIFT
LOGIC DIAGRAM
V CC = PIN 16
GND = PIN 8
1
LATCH
15
1
2
3
4
5
6
7
9
Q A
Q B
Q C
Q D
Q E
Q F
Q G
Q H
SQ H
OUTPUT
PARALLEL
OUTPUTS
SERIAL
DATA
DATA
REV 7
MC54/74HC595A
16
16
16
16
1
1
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
GND
ORDERING INFORMATION
1
Q C
Q D
Q G
Q H
Q B
Q E
1
Q F
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
CERAMIC PACKAGE
PLASTIC PACKAGE
TSSOP PACKAGE
16
15
14
13
12
10
SOIC PACKAGE
11
CASE 751B–05
CASE 948F–01
9
CASE 620–10
CASE 648–08
DT SUFFIX
N SUFFIX
D SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
TSSOP
V CC
Q A
A
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
SQ H

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MC54HC595AJ Summary of contents

Page 1

... The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 ...

Page 2

... Ceramic DIP: – from 100 _ to 125 _ C SOIC Package: – from 125 _ C TSSOP Package: – 6.1 mW from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 3

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

... High–Impedance State – NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Î Î Î Î ...

Page 5

... Q A – (Pins 15 Noninverted, 3–state, latch outputs (Pin 9) Noninverted, Serial Data Output. This is the output of the eighth stage of the 8–bit shift register. This output does not have three–state capability. 5 MC54/74HC595A Resulting Function Latch Serial Parallel Register Output Outputs Contents – Enabled ** * Z MOTOROLA ...

Page 6

... THL Figure 3. VALID SERIAL 50% INPUT LATCH 50% CLOCK Figure 5. TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 7. MOTOROLA SWITCHING WAVEFORMS V CC RESET GND t PHL OUTPUT SQ H SHIFT CLOCK OUTPUT V CC 50% ENABLE GND OUTPUT Q OUTPUT Q SHIFT CLOCK V CC ...

Page 7

... OUTPUT 13 ENABLE LATCH 12 CLOCK SERIAL 14 DATA INPUT A SHIFT 11 CLOCK 10 RESET High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM MC54/74HC595A PARALLEL DATA OUTPUTS SERIAL 9 DATA OUTPUT SQ H MOTOROLA ...

Page 8

... MC54/74HC595A SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT SQ H NOTE: implies that the output high–impedance state. MOTOROLA TIMING DIAGRAM 8 High–Speed CMOS Logic Data DL129 — Rev 6 ...

Page 9

... B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 1.27 BSC 0.050 BSC G J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 0.229 0.244 5.80 6.20 R 0.25 0.50 0.010 0.019 MOTOROLA ...

Page 10

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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