DS1215 Dallas Semiconductor, DS1215 Datasheet

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DS1215

Manufacturer Part Number
DS1215
Description
Phantom time chip
Manufacturer
Dallas Semiconductor
Datasheet

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DS1215
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DALLAS
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DS1215
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DS1215S
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FEATURES
DESCRIPTION
The DS1215 Phantom Time Chip is a combination of a
CMOS timekeeper and a nonvolatile memory controller.
In the absence of power, an external battery maintains
the timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of hun-
dredths of seconds, seconds, minutes, hours, day, date,
month, and year information. The last day of the month
is automatically adjusted for months with less than 31
days, including correction for leap year every four years.
The watch operates in one of two formats: a 12–hour
mode with an AM/PM indicator or a 24–hour mode. The
nonvolatile controller supplies all the necessary support
circuitry to convert a CMOS RAM to a nonvolatile
memory. The DS1215 can be interfaced with either
RAM or ROM without leaving gaps in memory.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
Keeps track of hundredths of seconds, seconds, min-
utes, hours, days, date of the month, months, and
years
Adjusts for months with fewer than 31 days
Leap year automatically corrected up to 2100
No address space required
Provides nonvolatile controller functions for battery
backup of RAM
Supports redundant batteries for high–reliability
applications
Uses a 32.768 KHz watch crystal
Full 10% operating range
Operating temperature range 0 C to 70 C
Space-saving, 16–pin DIP package and SOIC
Optional industrial temperature range –40 C to +85 C
(IND)
Copyright 1997 by Dallas Semiconductor Corporation.
PIN ASSIGNMENT
PIN DESCRIPTION
X1, X2
WE
BAT1
GND
D
Q
ROM/RAM
CEO
CEI
OE
RST
BAT2
V
V
NOTE: Both pins 5 and 8 must be grounded.
ORDERING INFORMATION
DS1215
DS1215S
DS1215N
DS1215SN
CCO
CCI
BAT1
GND
GND
WE
BAT1
GND
GND
X1
X2
WE
D
Q
X1
X2
D
Q
16–PIN SOIC (300 MIL)
– 32.768 KHz Crystal Connections
– Write Enable
– Battery 1 Input
– Ground
– Data In
– Data Out
– ROM/RAM Select
– Chip Enable Out
– Chip Enable Input
– Output Enable
– Reset
– Battery 2 Input
– Switched Supply Output
– +5 VDC Input
16–PIN DIP (300 MIL)
Phantom Time Chip
1
2
3
4
5
6
7
8
16–pin DIP
16–pin SOIC
16–pin DIP (IND)
16–pin SOIC (IND)
1
2
3
4
5
6
7
8
16
15
14
13
12
10
11
16
15
14
13
12
10
11
9
9
V
V
BAT2
RST
OE
CEI
CEO
ROM/RAM
V
V
BAT2
RST
OE
CEI
CEO
ROM/RAM
CCI
CCO
CCI
CCO
DS1215
032697 1/15
DS1215

Related parts for DS1215

DS1215 Summary of contents

Page 1

... Space-saving, 16–pin DIP package and SOIC Optional industrial temperature range – +85 C (IND) DESCRIPTION The DS1215 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory controller. In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM ...

Page 2

... DS1215 OPERATION The block diagram of Figure 1 illustrates the main ele- ments of the Time Chip. Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recog- nition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO) ...

Page 3

... CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the Time Chip. A 32,768 Hz quartz crystal can be directly connected to the DS1215 via pins 1 and 2 (X1, X2). The crystal se- lected for use should have a specified load capacitance (C L and crystal layout considerations, please consult Application Note 58, “ ...

Page 4

... BAT protection. During nominal supply conditions, CEO will track CEI with a maximum propagation delay of 20 ns. Internally, the DS1215 aborts any data transfer in prog- ress without changing any of the Time Chip registers and prevents future access until V typical RAM/Time Chip interface is illustrated in Figure 3 ...

Page 5

... ROM ADD V CC DATA I DS1215 CEO CCI 11 15 CEI V CCO 13 9 ROM/ RST RAM 4 14 BAT BAT 32.768 KHz D0 – VDC OR TIE TO GND FOR ONE–BATTERY OPERATION + BAT 2 D0 – VDC OR TIE TO GND FOR ONE–BATTERY OPERATION + BAT 2 DS1215 032697 5/15 ...

Page 6

... DS1215 TIME CHIP REGISTER DEFINITION Figure 5 REGISTER 12/ 032697 6/ 0.1 SEC 10 SEC 10 MIN A/P OSC RST DATE MONTH 10 YEAR 0.01 SEC SECONDS MINUTES HOUR DAY DATE MONTH YEAR RANGE (BCD) 00–99 00–59 00–59 01–12 00–23 01–07 01–31 01–12 00–99 ...

Page 7

... MIN TYP V 4 –0 2.5 BAT SYMBOL MIN TYP I CCI I CCO1 I –1 –1 –1 SYMBOL MIN TYP OH1 CCI V –0.2 BAT I BAT I CCO2 DS1215 ( MAX UNITS NOTES 4.5 to 5.5V) CC MAX UNITS NOTES + < 4.5V) CC MAX UNITS NOTES V 9 ...

Page 8

... DS1215 AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND PARAMETER Read Cycle Time CEI Access Time OE Access Time CEI to Output Low Output Low Z CEI to Output High Output High Z Read Recovery Write Cycle Write Pulse Width Write Recovery Data Setup Data Hold Time CEI Pulse Width ...

Page 9

... Recovery at Power–Up V Slew Rate 4.5 – 3.0V CC CCO SYMBOL MIN TYP t 120 COE t 10 OEE ODO 120 WC t 100 CW t 100 200 RST CCO SYMBOL MIN TYP t REC DS1215 ( 10%) CC MAX UNITS NOTES ns 100 ns 100 < 4.5V) CC MAX UNITS NOTES 032697 9/15 ...

Page 10

... DS1215 TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND CEI OE t COE Q TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND CEI D É É É É É É É É É É 032697 10/ OEE É É É OUTPUT DATA VALID É É É ...

Page 11

... OE Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç WE Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç D CCO OEE t COE OUTPUT DATA VALID CCO DATA IN STABLE ODO DS1215 032697 11/15 ...

Page 12

... DS1215 TIMING DIAGRAM: POWER DOWN CEI ROM/RAM = GND CEO ROM/RAM = V CEO CCO V CCI TIMING DIAGRAM: POWER UP ROM/RAM = GND CEO ROM/RAM = V CEO CCO V TIMING DIAGRAM: RESET FOR TIME CHIP RST 032697 12/ 4.5V V Ç Ç Ç Ç Ç Ç CEI Ç Ç Ç Ç Ç Ç ...

Page 13

... Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected low level as V falls below V CCI 10 the maximum average load current that the DS1215 can supply to memory in the battery backup mode. CC02 11. Applies to all input pins except RST. RST is pulled internally to V OUTPUT LOAD Figure 6 680 = 1 ...

Page 14

... DS1215 DS1215 TIME CHIP 032697 14/ PKG 16–PIN DIM MIN MAX A IN. 0.740 0.780 MM B IN. 0.240 0.260 MM C IN. 0.120 0.140 MM D IN. 0.300 0.325 MM E IN. 0.015 0.040 MM F IN. 0.110 0.140 MM G IN. 0.090 0.110 MM H IN. 0.300 0.370 MM J IN. 0.008 0.012 MM K IN. 0.015 0.021 MM ...

Page 15

... DS1215S SERIAL TIMEKEEPER 16–PIN SOIC PKG 16–PIN DIM MIN MAX A IN. 0.402 0.412 MM 10.21 10.46 B IN. 0.290 0.300 MM 7.37 7.65 C IN. 0.089 0.095 MM 2.26 2.41 E IN. 0.004 0.012 MM 0.102 0.30 F IN. 0.094 0.105 MM 2.38 2.68 G IN. 0.050 BSC MM 1.27 BSC H IN ...

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