S3098 AMCC (Applied Micro Circuits Corp), S3098 Datasheet
S3098
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S3098 Summary of contents
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... Fiber optic terminators • Fiber optic test equipment GENERAL DESCRIPTION The S3098 low power 1:16 receiver with Clock/Data Recovery (CDR) and integrated postamp is a fully inte- grated O C-192 des er ialization/clock and data recovery device. The S3098 receives an OC-192 scrambled NRZ serial signal and recovers the clock. ...
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... FEATURES.............................................................................................................................................................. 1 APPLICATIONS ...................................................................................................................................................... 1 GENERAL DESCRIPTION ...................................................................................................................................... 1 CONTENTS ............................................................................................................................................................. 2 FIGURES ................................................................................................................................................................. 3 TABLES ................................................................................................................................................................... 3 S3098 OVERVIEW .................................................................................................................................................. 4 Suggested Interface Devices ............................................................................................................................. 4 S3098 PIN DESCRIPTION ...................................................................................................................................... 6 Serial Data In (SERDATIP/N) ............................................................................................................................ 6 Reference Clock (REFCLKP/N) ........................................................................................................................ 6 Loop Filter (CAP1, CAP2) ................................................................................................................................. 6 Lock to Reference (LCKREFN) ......................................................................................................................... 6 Signal Detect (SDLVPECLN/SDLVCMOSN) ..................................................................................................... 6 Reset (RSTB) .................................................................................................................................................... 6 Factory Test (TSTSIG, TESTB) ......................................................................................................................... 6 Parallel Output Clock (POCLKP/N) ................................................................................................................... 7 Parallel Output Data (POUTP/N[15:0]) ...
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... Figure 8. S3098 LVDS Output to LVDS Input ........................................................................................................ 20 Figure 9. -5.2 V ECL Post Amp to S3098 Input DC Coupled Termination ............................................................. 20 Figure 10. -5.2 V ECL TIA to S3098 DC Coupled Termination .............................................................................. 21 Figure 11. +3.3 V Differential LVPECL Driver to S3098 LVPECL Reference Clock Input, AC Coupled Termination 21 Figure 12. External Loop Filter ............................................................................................................................... 21 Figure 13. Single-Ended Termination Scheme ...................................................................................................... 22 Table 1 ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp S3098 OVERVIEW The S3098 Clock and Data Recovery Unit (CDR) with Demultiplexer (DeMUX) implements SONET/SDH deserialization functions. Figure 2, Functional Block Diagram, shows the basic operation of the chip. This chip can be used to implement the front end of the SONET equipment, which consists primarily of the par- allel transmit interface and the serial receive interface ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Figure 2. Functional Block Diagram AMCC Confidential and Proprietary Revision NC - Oct 17, 2001 DEVICE SPECIFICATION 5 ...
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... The Serial Data In (SERDATIP/N) pins are differential Current Mode Logic (CML) inputs. They receive inputs from an optics module or other upstream logic device. The S3098 extracts the clock from the SERDATIP/N inputs and provides a recovered clock (POCLKP/N) with re-timed parallel data. These pins are internally biased and terminated 100 Ω ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Parallel Output Clock (POCLKP/N) The Parallel Output Clock (POCLKP/N) LVDS output is an internally regenerated clock which is used to transfer demultiplexed data from an internal holding register to the output register, which drives POUTP/N [15:0]. This ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp S3098 FUNCTIONAL DESCRIPTION Receiver Description The S3098 receiver chip provides the first stage of the digital processing of a receive SONET OC-192 bit- serial stream. It converts the bit-serial 9.953 Gbps data stream into a 622.08 Mbps (or equivalent FEC rate) 16-bit parallel data format ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 4. Input Pin Description and Assignment Pin Name Level I/O SERDATIP Diff. I SERDATIN CML REFCLKP Diff. I REFCLKN LVPECL CAP1 Analog I CAP2 LCKREFN LVCMOS I RSTB LVCMOS I TESTB LVCMOS I TSTSIG LVCMOS I SDLVPECLN Single- I Ended ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 5. Output Pin Descriptions and Assignment Pin Name Level I/O POCLKP LVDS O POCLKN POUT0P LVDS O POUT0N POUT1P POUT1N POUT2P POUT2N POUT3P POUT3N POUT4P POUT4N POUT5P POUT5N POUT6P POUT6N POUT7P POUT7N POUT8P POUT8N ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 6. Common Pin Descriptions and Assignment Pin Name Level I/O COREVCC +2.5 V PWR LVDSVCC +2.5 V PWR LVCMOSVCC +2.5 V PWR CMLVEE -5.2 V PWR SUBVEE -5.2 V PWR ANALOG AVCC +3.3 V PWR DIGITALVCC +3.3 V PWR ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Figure 3. S3098 Pinout (Top View ANALOG AVCC A ANALOG ANALOG ANALOG +3.3V GND GND GND (FILTER) REFCLKP ANALOG CAP1 B ANALOG GND GND ANALOG ANALOG C REFCLKN CAP2 GND GND CML ANALOG D VEE GND -5.2V ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Figure 4. Compact 148-pin CBGA Package Table 7. Package Thermals Max Package Power (85°C Ambient) (Assuming 125°C Junction Temp) 1.95 W AMCC Confidential and Proprietary Revision NC - Oct 17, 2001 DEVICE SPECIFICATION Θja 20.5°C/Watt Θjc 3.0° ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 8. Performance Specifications Parameter Nominal VCO Center Frequency 155.52 MHz (or equivalent FEC rate) Reference Clock Frequency Toler- ance 155.52 MHz (or equivalent FEC rate) Reference Clock Input Duty Cycle 155.52 MHz (or equivalent FEC rate) ...
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... Table 9. Absolute Maximum Ratings The following are the absolute maximum stress ratings for the S3098 device. Stresses beyond those listed may cause permanent damage to the device. Absolute maximum ratings are stress ratings only, and operation of the device at the maximums stated or any other conditions beyond those indicated in the “ ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 10. Recommended Operating Conditions Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage on V with Respect to GND CC_2.5 V Voltage on V with Respect to GND CC_3.3 V Voltage on V with Respect to GND EE I Supply Current CC_2 ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 12. LVDS Output Characteristics Parameter Description V Output High Voltage OH V Output Low Voltage OL V Output Differential ODIFF Voltage V Output Single- OSINGLE ended Voltage R Differential Output ODIFF Impedance Table 13. Internally Biased Differential LVPECL Input DC Characteristics (REFCLKP/N) ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Table 15. LVCMOS Input DC Characteristics Parameter Description V Input High Voltage IH V Input Low Voltage IL I Input High Current IH I Input Low Current IL Table 16. LVCMOS Output DC Characteristics Parameter Description V Output High Voltage OH V Output Low Voltage OL Table 17 ...
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... 525 ps POCLK duty cycle variation = ± 74 OIF Specification(S3098 meets and exceeds 185 ps PD POUT receiving side setup/hold time for OIF compliance = ± 200 ps 1. When a setup time is specified on LVDS signals between an input and a clock, the setup time in picoseconds, is from the 50% point of the input to the 50% point of the clock ...
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... Figure 7. Single-Ended Data Input Voltage Measurement V(+) WRT GND 0 V Figure 8. S3098 LVDS Output to LVDS Input +2.5 V 330 Ω 330 Ω S3098 LVDS Output Figure 9. -5.2 V ECL Post Amp to S3098 Input DC Coupled Termination 0 V -5.2 V S3196 POST AMPLIFIER 20 Revision NC - Oct 17, 2001 DEVICE SPECIFICATION V ISINGLE +2 +3 Ω ...
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... Low Power Receiver w/CDR/Postamp Figure 10. -5.2 V ECL TIA to S3098 DC Coupled Termination 0 V -5.2 V S3090 Transimpendance Amplifier Figure 11. +3.3 V Differential LVPECL Driver to S3098 LVPECL Reference Clock Input, AC Coupled Termination +3 LVPECL REFCLK Output Figure 12. External Loop Filter (See Table 18, External Loop Filter Components) ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Figure 13. Single-Ended Termination Scheme (Termination Scheme that was characterized -5 See S3098 Single-Ended Termination Recommendation Application Note for more details and improvement of input sensitivity. 22 Revision NC - Oct 17, 2001 DEVICE SPECIFICATION BIAS Ω P 100 Ω ...
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... S3098 – SONET/SDH/ATM OC-192 1:16 Low Power Receiver w/CDR/Postamp Prefix S – Integated Circuit Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...