S2060C AMCC (Applied Micro Circuits Corp), S2060C Datasheet

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S2060C

Manufacturer Part Number
S2060C
Description
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

Specifications of S2060C

Case
TQFP
Dc
03+

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Part Number:
S2060C
Quantity:
12 590
March 7, 2001 / Revision H
FEATURES
APPLICATIONS
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
GIGABIT ETHERNET TRANSCEIVER
GIGABIT ETHERNET TRANSCEIVER
• Operating rate
• 1250 MHz (Gigabit Ethernet) line rates
• Half and full VCO output rates
• Functionally compliant IEEE 802.3z Gigabit
• Transmitter incorporating Phase-Locked Loop
• Receiver PLL provides clock and data recovery
• 10-bit parallel TTL compatible interface
• Low-jitter serial LVPECL compatible interface
• Local loopback
• Single +3.3 V supply, 620 mW power dissipation
• 64 PQFP or TQFP package
• Continuous downstream clocking from receiver
• Drives 30 m of Twinax cable directly
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
Ethernet standard
(PLL) clock synthesis from low speed reference
Controller
Ethernet
Gigabit
S2060
Optical
Tx
Optical
Rx
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Optical
Rx
Optical
Tx
S2060
Controller
Ethernet
Gigabit
S2060
S2060
®
1

Related parts for S2060C

S2060C Summary of contents

Page 1

DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER FEATURES • Operating rate • 1250 MHz (Gigabit Ethernet) line rates • Half and full VCO output rates • Functionally compliant IEEE 802.3z Gigabit Ethernet standard • Transmitter incorporating Phase-Locked Loop (PLL) ...

Page 2

S2060 S2060 OVERVIEW The S2060 transmitter and receiver provide serial- ization and deserialization functions for block en- coded data to implement a Gigabit Ethernet interface. The S2060 functional block diagram is de- picted in Figure 2. The sequence of operations ...

Page 3

GIGABIT ETHERNET TRANSCEIVER TRANSMITTER DESCRIPTION The S2060 transmitter accepts 10-bit parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the IEEE 802.3z Gigabit Ethernet standard, and supports the ...

Page 4

S2060 RECEIVER DESCRIPTION Whenever a signal is present, the receiver attempts to recover the serial clock from the received data stream. The S2060 searches the serial bit stream for the occurrence of a positive polarity COMMA sync pattern (0011111xxx positive ...

Page 5

GIGABIT ETHERNET TRANSCEIVER The COM_DET output signal is ACTIVE whenever EN_CDET is active and the COMMA control charac- ter is present on the RX[0:9] parallel data outputs. The COM_DET output signal will be INACTIVE at all other times. Parallel Output ...

Page 6

S2060 Table 5. Pin Description and Assignment ...

Page 7

GIGABIT ETHERNET TRANSCEIVER Table 5. Pin Description and Assignment (Continued ...

Page 8

S2060 Table 6. Power and Ground Signals ...

Page 9

GIGABIT ETHERNET TRANSCEIVER Figure 3. S2060 Pinout (S2060A, S2060B, S2060D) 1 VEE 2 TX[0] TX[ TX[2] VCC 5 6 TX[3] TX[4] 7 TX[ TX[6] VCC 10 TX[7] 11 TX[ TX[9] RATEN 14 15 AVEE ...

Page 10

... S2060 Figure 4. S2060 Pinout (S2060C) 1 VEE 2 TX[0] TX[ TX[2] VCC 5 6 TX[3] TX[4] 7 TX[ TX[6] VCC 10 11 TX[7] TX[ TX[9] RATEN 14 15 AVEE 16 TC1 Thermal Management GIGABIT ETHERNET TRANSCEIVER S2060C TOP VIEW ...

Page 11

GIGABIT ETHERNET TRANSCEIVER Figure 5. 10mm x 10mm 64 PQFP Package (S2060A) TOP VIEW March 7, 2001 / Revision H S2060 11 ...

Page 12

S2060 Figure PQFP Package (S2060B) TOP VIEW 12 GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H ...

Page 13

... GIGABIT ETHERNET TRANSCEIVER Figure 7. 10mm x 10mm 64 TQFP Package (S2060C) TOP VIEW March 7, 2001 / Revision H S2060 13 ...

Page 14

S2060 Figure PQFP Package (S2060D) TOP VIEW 14 GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H ...

Page 15

GIGABIT ETHERNET TRANSCEIVER Table 7. Power and Ground Application Information ...

Page 16

S2060 Figure 9. Power and Ground Connection Diagram 0.1 F 100 (+3.3 V) Vcc (+3 (+3 ferrite 100 pF 0 GIGABIT ETHERNET TRANSCEIVER V CC (+3.3 V) ...

Page 17

GIGABIT ETHERNET TRANSCEIVER Figure 10. Transmitter Timing TBC TX[0-9] SERIAL DATA OUT Table 8. S2060 Transmitter Timing ...

Page 18

S2060 Figure 12. Receiver Timing Half Rate Mode (RATEN Inactive) SERIAL DATA IN RBC1 RX[9-0] Table 9. S2060 Receiver Timing ...

Page 19

... Commercial temperature range S2060A, S2060B, S2060C. 2. Industrial temperature range S2060D. March 7, 2001 / Revision H absolute maximum rating conditions for extended periods may affect ...

Page 20

S2060 Table 12. Reference Clock Requirements ...

Page 21

GIGABIT ETHERNET TRANSCEIVER OUTPUT LOAD The S2060 serial outputs require a resistive load to set the output current. The recommended resistor value is 150 to ground. This value can be varied to adjust drive current, signal voltage swing, and power ...

Page 22

S2060 Ordering Information Applied Micro Circuits Corporation • 6290 Sequence Dr., San ...

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