PM49FL004T-33JC PMC-Sierra Inc, PM49FL004T-33JC Datasheet

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PM49FL004T-33JC

Manufacturer Part Number
PM49FL004T-33JC
Description
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
Manufacturer
PMC-Sierra Inc
Datasheet

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FEATURES
Programmable Microelectronics Corp.
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
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PMC
Single Power Supply Operation
Low voltage range: 3.0 V - 3.6 V
Standard Intel Firmware Hub/LPC Inter-
face
Read compatible to Intel
Hub devices
Conforms to Intel LPC Interface Specification
Revision 1.1
Memory Configuration
Pm49FL002: 256K x 8 (2 Mbit)
Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Top Boot Block
Pm49FL002: 16 Kbyte top Boot Block
Pm49FL004: 64 Kbyte top Boot Block
Automatic Erase and Program Operation
Build-in automatic program verification for
extended product endurance
Typical 25 µs/byte programming time
Typical 50 ms sector/block/chip erase time
Two Configurable Interfaces
In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
®
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
82802 Firmware
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Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
33 MHz synchronous operation with PCI bus
5-signal communication interface for in-
system read and write operations
Standard SDP Command Set
Data# Polling and Toggle Bit features
Register-based read and write protection for
each block (FWH mode only)
4 ID pins for multiple Flash chips selection
(FWH mode only)
5 GPI pins for General Purpose Input Register
TBL# pin for hardware write protection to Boot
Block
WP# pin for hardware write protection to whole
memory array except Boot Block
Address/Address Multiplexed (A/A Mux)
Mode
11-pin multiplexed address and 8-pin data I/O
interface
Supports fast programming on EPROM
programmers
Standard SDP Command Set
Data# Polling and Toggle Bit features
Lower Power Consumption
Typical 2 mA active read current
Typical 7 mA program/erase current
High Product Endurance
Guarantee 100,000 program/erase cycles per
single sector (preliminary)
Minimum 20 years data retention
Compatible Pin-out and Packaging
32-pin (8 mm x 14 mm) VSOP
32-pin PLCC
Optional lead-free (Pb-free) package
Hardware Data Protection
Pm49FL002 / Pm49FL004
Issue Date: December, 2003 Rev:1.4

PM49FL004T-33JC Summary of contents

Page 1

PMC 2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory FEATURES • Single Power Supply Operation - Low voltage range: 3 3.6 V • Standard Intel Firmware Hub/LPC Inter- face ® - Read compatible to Intel ...

Page 2

PMC GENERAL DESCRIPTION The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to ...

Page 3

PMC CONNECTION DIAGRAMS FWH LPC A/A Mux GPI1 GPI1 GPI0 GPI0 TBL# TBL# ID3 ID2 ID1 ID0 LAD0 ...

Page 4

PMC PRODUCT ORDERING INFORMATION Pm49FL00x T - ...

Page 5

PMC PIN DESCRIPTIONS ...

Page 6

PMC BLOCK DIAGRAM TBL INIT# FWH[3:0] or LAD[3: FWH4 or LFRAME CLK GPI[4:0] A[10:0] I/O[7: ...

Page 7

PMC DEVICE OPERATION (CONTINUED) The Pm49FL002/004 provide three levels of data protec- tion for the critical BIOS code of PC and Notebook. It includes memory hardware write protection, hardware data protection and software data protection. MEMORY HARDWARE WRITE PROTECTION The ...

Page 8

PMC DEVICE OPERATION (CONTINUED) SECTOR AND BLOCK ERASE The Pm49FL002 contains sixty-four uniform 4 Kbyte sec- tors, or sixteen uniform 16 Kbyte blocks (sector group - consists of four adjecent sectors). The Pm49FL004 con- tains one hundred and twenty-eight uniform ...

Page 9

PMC FWH MODE OPERATION FWH MODE MEMORY READ/WRITE OPERATION In FWH mode, the Pm49FL002/004 are connected through a 5-pin communication interface - FWH[3:0] and ® FWH4 pins to work with Intel Family of I/O Controller Hubs (ICH) chipset platforms. The ...

Page 10

PMC FWH MODE OPERATION (CONTINUED) Table 2: FWH Memory Read Cycle Definition ...

Page 11

PMC FWH MODE OPERATION (CONTINUED) Table 3: FWH Memory Write Cycle Definition ...

Page 12

PMC FWH MODE OPERATION (CONTINUED) FWH BYTE PROGRAM WAVEFORMS CLK RST# or INIT Memory Write IDSEL Cycle FWH[3:0] 1110b ID[3:0] 1 Clock 1 Clock CLK RST# or INIT 2nd Start IDSEL FWH[3:0] ...

Page 13

PMC FWH SECTOR ERASE WAVEFORMS RST# or INIT Memory Write Cycle IDSEL 1110b ID[3:0] 1 Clock 1 Clock RST# or INIT# F ...

Page 14

PMC FWH BLOCK ERASE WAVEFORMS RST# or INIT Memory Write Cycle IDSEL 1110b ID[3:0] 1 Clock 1 Clock RST# or INIT# F ...

Page 15

PMC FWH MODE OPERATION (CONTINUED) FWH GPI REGISTER READ WAVEFORMS CLK RST# or INIT Memory Read Cycle FWH[3:0] 1101b 1 Clock FWH BLOCK LOCKING REGISTER READ WAVEFORMS CLK RST# or INIT Memory ...

Page 16

PMC LPC MODE OPERATION LPC MODE MEMORY READ/WRITE OPERATION In LPC mode, the Pm49FL002/004 use the 5-pin LPC interface includes 4-bit LAD[3:0] and LFRAME# pins to communicate with the host system. The addresses and data are transmitted through the 4-bit ...

Page 17

PMC LPC MODE OPERATION (CONTINUED ...

Page 18

PMC LPC MODE OPERATION (CONTINUED) Table 5: LPC Memory Write Cycle Definition ...

Page 19

PMC LPC MODE OPERATION (CONTINUED) LPC BYTE PROGRAM WAVEFORMS CLK RST# or INIT Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CLK RST# or INIT ...

Page 20

PMC LPC SECTOR ERASE WAVEFORMS RST# or INIT Memory 1st Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock RST# or INIT ...

Page 21

PMC LPC BLOCK ERASE WAVEFORMS RST# or INIT Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock RST# or INIT ...

Page 22

PMC LPC MODE OPERATION (CONTINUED) LPC GPI REGISTER READ WAVEFORMS CLK RST# or INIT# LFRAME# Start LAD[3:0] 0000b 1 Clock Programmable Microelectronics Corp. Memory Read Address Cycle 1111b 1100b 010Xb 1111b 1011b 0000b 0001b 1 Clock Load Address "FFBC0100h" in ...

Page 23

PMC REGISTERS The Pm49FL002/004 have two registers include the Gen- eral Purpose Inputs Register (GPI_REG - available in FWH and LPC modes) and the Block Locking Register (BL_REG - available in FWH mode only). The GPI_REG can be read at ...

Page 24

PMC REGISTERS (CONTINUED) Table 7. Block Locking Register Definition " " ...

Page 25

PMC REGISTERS (CONTINUED) Table 8. Pm49FL002 Block Locking Register Address ...

Page 26

PMC A/A MUX MODE OPERATION A/A MUX MODE READ/WRITE OPERATION The Pm49FL002/004 offers a Address/Address Multi- plexed (A/A Mux) mode for off-system operation, typi- cally on an EPROM Programmer, similar to a traditional Flash memory except the address input is ...

Page 27

PMC SYSTEM MEMORY MAP System Memory (Top 4 MBytes) FFFFFFFFh FFFC0000h FFF80000h FFF00000h FFC00000h Programmable Microelectronics Corp. Pm49FL002 (2 Mbits) Pm49FL004 (4 Mbits) Range for other FWH Devices Table 11. System Memory Map 27 Pm49FL002 / 004 Pm49FL008 (8 Mbits) ...

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PMC MEMORY BLOCKS AND ADDRESSES Table 12. Pm49FL002 Sector/Block Address Table ...

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PMC MEMORY BLOCKS AND ADDRESSES (CONTINUED) Table 13. Pm49FL004 Sector/Block Address Table ...

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PMC COMMAND DEFINITION Table 14. Software Data Protection Command Definition ...

Page 31

PMC DEVICE OPERATIONS FLOWCHARTS AUTOMATIC PROGRAMMING Programmable Microelectronics Corp. Start Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data A0h Address to Increment Address 5555h Load Program Data to Program Address I/O7 = Data? or ...

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PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) AUTOMATIC ERASE CHIP ERASE COMMAND Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data 80h to Address 5555h Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh ...

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PMC DEVICE OPERATIONS FLOWCHARTS (CONTINUED) SOFTWARE PRODUCT IDENTIFICATION ENTRY Load Data AAh to Address 5555h Load Data 55h to Address 2AAAh Load Data 90h to Address 5555h Enter Product Identification (1,2) Mode Notes: 1. After entering Product Identification Mode, the ...

Page 34

PMC ABSOLUTE MAXIMUM RATINGS ...

Page 35

PMC DC CHARACTERISTICS ...

Page 36

PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE AC INPUT/OUTPUT CHARACTERISTICS ...

Page 37

PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INTERFACE CLOCK WAVEFORM FWH/LPC INTERFACE MEASUREMENT CONDITION PARAMETERS ...

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PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC INPUT TIMING PARAMETERS FWH[3:0] or LAD[3:0] (Valid Input Data) FWH/LPC OUTPUT TIMING PARAMETERS FWH[3:0] or LAD[3:0] (Valid Output Data) FWH[3:0] or LAD[3:0] (Float Output Data) Programmable Microelectronics Corp. V ...

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PMC AC CHARACTERISTICS (CONTINUED) FWH/LPC RESET OPERATION CHARACTERISTICS ...

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PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE READ OPERATIONS CHARACTERISTICS ...

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PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS ...

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PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE BYTE PROGRAM OPERATIONS AC WAVEFORMS 5555 R/ A/A MUX MODE ...

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PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE SECTOR/BLOCK ERASE OPERATIONS AC WAVEFORMS 5555 R/ DATA A/A MUX MODE TOGGLE BIT ...

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PMC AC CHARACTERISTICS (CONTINUED) A/A MUX MODE DATA# POLLING AC WAVEFORMS R/ I/O7 Note: ...

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PMC PACKAGE TYPE INFORMATION 32V 32-Pin Thin Small Outline Package (VSOP - mm)( measure in millimeters) Pin 1 I. 32J 32-Pin Plastic Leaded Chip Carrier ...

Page 46

PMC REVISION HISTORY ...

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