PM4314-RI PMC-Sierra Inc, PM4314-RI Datasheet

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PM4314-RI

Manufacturer Part Number
PM4314-RI
Description
Quad T1/E1 line interface device
Manufacturer
PMC-Sierra Inc
Datasheet

Specifications of PM4314-RI

Case
QFP
Dc
00+

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PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
PM4314
QDSX
QUAD T1/E1 LINE INTERFACE DEVICE
DATA SHEET
ISSUE 5: JUNE 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Related parts for PM4314-RI

PM4314-RI Summary of contents

Page 1

... DATA SHEET PMC-950857 QUAD T1/E1 LINE INTERFACE DEVICE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX DATA SHEET ISSUE 5: JUNE 1998 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ...

Page 2

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Details of Change Data Sheet Reformatted — No Change in Technical Content Generated R5 data sheet from PMC-950739, R4 Eng Doc Issue R3 released Public release of document: removal of confidential notices Upgrade to Eng Doc Issue P2 Creation of Document PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ...

Page 3

... PSEUDO-RANDOM BIT SEQUENCE GENERATOR (PRSG)..... 42 9.8 INBAND LOOPBACK CODE GENERATOR (XIBC)..................... 43 9.9 B8ZS/HDB3/AMI LINE ENCODER (LCODE) .............................. 43 9.10 DIGITAL JITTER ATTENUATOR (DJAT)....................................... 43 9.11 ANALOG PULSE GENERATOR (XPLS)...................................... 49 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE i ...

Page 4

... JTAG SUPPORT ........................................................................ 130 13 FUNCTIONAL TIMING ......................................................................... 141 13.1 LINE CODE VIOLATION INSERTION ....................................... 141 14 ABSOLUTE MAXIMUM RATINGS........................................................ 144 15 CAPACITANCE ..................................................................................... 145 16 D.C. CHARACTERISTICS .................................................................... 146 17 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 149 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ii ...

Page 5

... DATA SHEET PMC-950857 18 A.C. TIMING CHARACTERISTICS ....................................................... 153 19 ORDERING AND THERMAL INFORMATION ...................................... 163 20 MECHANICAL INFORMATION............................................................. 164 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE iii ...

Page 6

... ENABLE/STATUS ................................................................................... 81 REGISTERS 01AH-01BH, 05AH-05BH, 09AH-09BH, 0DAH-0DBH: LATCHING LCV PERFORMANCE DATA .................................................................. 82 REGISTERS 01AH, 05AH, 09AH AND 0DAH: LCV_PMON LINE CODE VIOLATION COUNT LSB ....................................................................... 83 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE iv ...

Page 7

... REGISTER 02DH, 06DH, 0ADH, 0EDH: XPLS CONTROL/STATUS .............. 106 REGISTER 02EH, 06EH, 0AEH, 0EEH: XPLS CODE INDIRECT ADDRESS 108 REGISTER 02FH, 06FH, 0AFH, 0EFH: XPLS CODE INDIRECT DATA.......... 110 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE v ...

Page 8

... DATA SHEET PMC-950857 REGISTER 030H, 070H, 0B0H, 0F0H: RSLC CONFIGURATION .................. 111 REGISTER 031H, 071H, 0B1H, 0F1H: RSLC INTERRUPT ENABLE/STATUS112 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE vi ...

Page 9

... FIGURE 16- EXTERNAL ANALOG TRANSMIT INTERFACE CIRCUIT ........... 51 FIGURE 17- TIMING OPTIONS ........................................................................ 75 FIGURE 18- CODE REGISTER SEQUENCE DURING PULSE GENERATION ..................................................................................................... 125 FIGURE 19- CODE REGISTER SEQUENCE FOR 0-110 FEET BUILD-OUT 126 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE vii ...

Page 10

... FIGURE 34- XCLK INPUT TIMING DIAGRAM (FIFO NOT IN TX PATH) ........ 157 FIGURE 35- RCLKO OUTPUT TIMING DIAGRAM......................................... 158 FIGURE 36- JTAG PORT INTERFACE TIMING.............................................. 160 FIGURE 37- ANALOG RECEIVE DATA INPUT TIMING DIAGRAM................ 161 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE viii ...

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... TABLE 18 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 30) ..................................................................................................... 151 TABLE 19 - XCLK INPUT FOR JITTER ATTENUATION (FIGURE 31).......... 153 TABLE 20 - TCLKI INPUT TIMING (FIGURE 32)........................................... 154 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ix ...

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... TABLE 24 - JTAG PORT INTERFACE TIMING (FIGURE 36) ........................ 159 TABLE 25 - ANALOG RECEIVE DATA INPUT TIMING (FIGURE 37) ........... 161 TABLE 26 - QDSX ORDERING INFORMATION ........................................... 163 TABLE 27 - QDSX THERMAL INFORMATION.............................................. 163 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE x ...

Page 13

... Slices incoming G.703 DSX-1 and CEPT E1 bipolar line signals into digital return-to-zero (RZ) pulses. Selectable slicer levels (DSX-1/CEPT E1) to provide improved SNR. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 1 ...

Page 14

... Optionally allows jitter attenuation of recovered clock and data, using bit FIFO. Optionally inserts unframed inband code sequences in place of recovered data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE -2 bit 2 ...

Page 15

... Accepts either dual rail or single rail DS-1/E1 signals. Performs B8ZS or AMI encoding when processing a single rail DS-1 signal and HDB3 or AMI encoding when processing a single rail E1 signal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 3 ...

Page 16

... Optionally detects inband code sequences in DS-1 transmit streams. Optionally inserts unframed test sequences in place of input transmit data. Optionally detects unframed test sequences in the input transmit data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 4 ...

Page 17

... ATM interfaces Electronic DSX-1/CEPT E1 Cross-connects Digital Access and Cross-connect Systems (DACS) Multiplexers Channel Service Units (CSUs) DSX-1/CEPT E1 Repeaters Test Equipment PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 5 ...

Page 18

... Bell Communications Research, TR-TSY-000499 - "Transport Systems Generic Requirements (TSGR): Common Requirement", Issue 3, December, 1989. 12. AT&T, TR 43801 - "Digital Channel Bank - Requirements and Objectives", November, 1982. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 6 ...

Page 19

... Monitoring on 2048, 8448, 34368, and 139264 kbit/s Signals", Rev.1, Oct. 1992. 24. ITU-T, Recommendation I.432 - “B-ISDN User-Network Interface - Physical Layer Specification”, August 1992. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 7 ...

Page 20

... G en eric M icrop roce ssor B us Example 1 shows the PM4314 QDSX used with the PM7344 S/UNI-MPH to implement a quad T1/E1 UNI where the DS1 or E1 signals are presented on DSX electrical interfaces. In this example, the DSX line interface functions are provided by the QDSX and the DS framing functions are provided by the S/UNI-MPH ...

Page 21

... S/UNI-MPH. If jitter attenuation is not required by either device, then an 8X reference clock may be supplied to both devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 9 ...

Page 22

... ISSUE 5 74HC T1 75 pack T[ T[ T[ T[ T[ T[ T[ LK2X PM 4344 4314 *note atten uation netw ork s not show n PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 10 ...

Page 23

... DATA SHEET PMC-950857 Example 2 shows a DSX 1/0 Cross-Connect using a PM4314 QDSX, a PM4344 TQUAD, and a Digital Time/Space Switch to implement a simple 1/0 cross- connect. An alternate architecture could use two Digital Time/Space Switches, one as a voice switch and the other as a signaling switch, and 2 TQUADs to cross-connect eight T1s. (Note: a true implementation would require redundancy in the switch core ...

Page 24

... From circu itry Example 3 shows the use of the PM4314 QDSX with the PM8313 D3MX in an M13 Multiplexer/Demultiplexer application. Use of the SSI LIU as illustrated requires that TICLK of the D3MX has a duty cycle of 45% min., 55% max. or better (e.g.. using a Connor Winfield S65T3 reference oscillator). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ ...

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... IN - BAN D LOOP- BAC Mic ro p roce terfa rdw tro als PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE TIP [ JAT ...

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... BAC ETEC Micro rfa rdw trol Sign a ls PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE TXTI P JAT ...

Page 27

... PMC-950857 6 DESCRIPTION The PM4314 QDSX Quad T1/E1 Line Interface Device is a monolithic integrated circuit that supports DSX-1 and CEPT E1 compatible transmit and receive interfaces for four 1.544 Mbit/s or 2.048 Mbit/s data streams. In the incoming direction, the DSX-1/E1 signals for each quadrant of the QDSX are first processed by a receive data slicer ...

Page 28

... PRBS data from the unipolar input transmit data stream. The QDSX operates in conjunction with external line coupling transformers, resistors, and capacitors. An external crystal may be used for high speed timing PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 16 ...

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... DATA SHEET PMC-950857 generation. The QDSX is configured, controlled, and monitored using registers that are accessed via a generic microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 17 ...

Page 30

... VSSI[5] PIN 38 PIN 39 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX Top View PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE PIN 103 PIN 102 VSSI[13] RDUAL RDD[1]/RDP[1]/SDP[1] RLCV[1]/RDN[1]/SDN[1] RCLKO[1] RDD[2]/RDP[2]/SDP[2] ...

Page 31

... Transmit Reference Decoupling Capacitor (TC[4:1]). These analog bidirectionals provide 44 decoupling for an internal reference generator. 108 They must be connected to an external decoupling capacitor to the corresponding 123 TAVD[4:1]. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 19 ...

Page 32

... Receive Bipolar Ring (RXRING[4:1]). The RXRING[4:1] bidirectional pins provide DC bias external isolation transformer. They must 104 be connected to the negative lead of the transformer secondary and to a decoupling 127 capacitor to RAVS[4:1]. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 20 ...

Page 33

... RDP[4:1] outputs can be updated on either the falling or rising RCLKO[4:1] edge. Sliced Positive Line Pulse (SDP[4:1]). A positive pulse on the SDP[4:1] outputs corresponds to the sampled positive pulse excursion on the RXTIP[4:1] input. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 21 ...

Page 34

... MHz for T1, 49.152 MHz for E1). When jitter attenuation is not required, XCLK can be driven clock (12.352 MHz for T1, 16.384 MHz for E1). Vector Clock (VCLK). The VCLK signal is used during QDSX production test to verify internal functionality. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 22 ...

Page 35

... When TDUAL is set high, the TDP[4:1] and TDN[4:1] inputs are enabled. When both the TDUAL input pin and register bits are set low, then the TDD[4:1] inputs are enabled and the TDN[4:1] inputs are ignored. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 23 ...

Page 36

... CSB is low. Active low Read Enable (RDB). This signal is pulsed low to enable a QDSX register read access. The QDSX drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 24 ...

Page 37

... Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active unmasked interrupt sources are acknowledged at their source. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 25 ...

Page 38

... Test Data Output (TDO). This signal carries test data out of the QDSX via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 26 ...

Page 39

... Pad Ring Ground Pins (VSSO[6:1]). These pins must be connected to a common ground together 111 with the VSSI[15:1], TAVS[4:1], and RAVS[4:1] 93 pins. Care must be taken to avoid coupling noise between these pins PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 27 ...

Page 40

... TAVS[4:1] must be 114 connected to a common ground together with the VSSO[6:1], VSSI[15:1], and RAVS[4:1] pins. 117 Care must be taken to avoid coupling noise between these pins. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 28 ...

Page 41

... These power supply connections must all be utilized and must all connect to a common + ground rail, as appropriate. There is no low impedance connection within the PM4314 QDSX between the core, pad ring, transmit analog, and receive analog supply rails. Failure to properly make these connections may result in improper operation or damage to the device ...

Page 42

... VDDO[6:1] must be less than 0.5 volt. The relative power sequencing of TAVD[4:1] and RAVD[4:1] power supplies is not important. 5.4 Power down the device in the reverse sequence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 30 ...

Page 43

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 twisted pair, or G.703 75 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE coax. 31 ...

Page 44

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Turns R1 Ratio ( ± 1%) (N ± 5%) 2 357 2 205 2 309 2 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE R2 Squelch Level at ( ± 1%) Primary (mV Typical) 121 276 95.3 220 93 227 402 50 ...

Page 45

... Many manufacturers have standard products for these applications. Typical characteristics of a suitable transformer are given in the following table. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 R1 1:N 0.1 µF ± 10% 316 k ±1% PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE V DD RAVD RXTIP R2 RXRING RC ...

Page 46

... When the CDRC is disabled, the positive and negative sliced PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 C (pF L (µH w/w L max.) max.) 35 0.80 is the inter-winding capacitance, w/w is the leakage inductance, and L PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE DCR pri. DCR sec. ( max.) ( max.) 0.80 1.2 34 ...

Page 47

... The DSX-1 jitter tolerance with ALGSEL set to 1 and shown in Figure 7. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 20 -1 with 14 zero restriction). 35 ...

Page 48

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 IN SPEC. REGION CDRC MAX. TOLERANCE (ALGSEL=0) 0.70 SINEWAVE JITTER FREQUENCY, kHz - LOG SCALE 15 -1 sequence. The E1 jitter tolerance PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE CDRC MAX. TOLERANCE (ALGSEL=1) AT&T SPEC. BELLCORE SPEC. 100 10 36 ...

Page 49

... DATA SHEET PMC-950857 Figure jitter tolerance with ALGSEL = 1 Measurement Limit 10 1.0 G823 Jitter Tolerance Specification 0.1 0.01 . PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Jitter Frequency (Hz) PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Measured CDRC Jitter Tolerance (ALGSEL = 1) 37 ...

Page 50

... OVR register bit in the LCV_PMON Interrupt Enable/Status register (014H, 054H, 094H, and 0D4H) is asserted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 G823 Jitter Tolerance Specification Jitter Frequence (Hz) PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Measured CDRC Jitter Tolerance (ALGSEL = 0) 38 ...

Page 51

... PRSM will lose synchronization in 48 µsec (for DSX- µsec (for E1), more than 99% of the time. In the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 39 ...

Page 52

... XCLK by 3. This 8X clock will be presented on CLKO8X. Otherwise, XCLK is expected high speed clock and TOPS will simply buffer it before passing it off as the internal high speed PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 40 ...

Page 53

... The Digital Jitter Attenuator (DJAT) function is used to attenuate jitter in the transmit clock when required. The DJAT block receives jittered data and stores PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 41 ...

Page 54

... DSX-1 interface with a worst case frequency offset of 354 Hz. The input jitter tolerance is 35 UIpp for an E1 interface with a worst case frequency offset PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 42 ...

Page 55

... These tolerances are shown in Figure 10 and Figure 11. Figure 10 - DSX-1 Jitter Tolerance 100 28 10 Jitter Amplitude, UIpp 1.0 0.1 0.01 1 4.9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 10 100 0.3k 1k Jitter Frequency, Hz PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE DJAT minimum tolerance acceptable unacceptable 10k 100k 43 29 0.2 ...

Page 56

... PLL reference clock and XCLK ÷ 24 are shown in Figure 12 and Figure 13. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 ITU -T G.82 3 unacce ptab le Region 2 0 100 1k J itter F req uency, Hz PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE tolerance a cce pta b le 0.2 2. ...

Page 57

... Max frequency 30 100 offset (PLL Ref to XCLK) 0 XCLK Accuracy PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 200 250 0 32 200 49 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 300 354 Hz 100 ± ppm 42.4 39 34.9 300 308 Hz 100 ± ...

Page 58

... Figure 14 and Figure 15. Figure 14 - DSX-1 Jitter Transfer 0 -10 62411 min -20 Jitter Gain (dB) -30 -40 -50 1 6.6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 62411 max DJAT response 10 100 Jitter Frequency, Hz PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 43802 max 1k 10k 46 ...

Page 59

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE JAT 100 Jitter F re quenc coaxial lines are given in the Operations PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE U nac c epta ble -19 .5 10k 47 ...

Page 60

... TAIS bit is set high in the XPLS Control/Status register (02DH, 06DH, 0ADH, and 0EDH). This AIS generation may optionally be enabled when internal loopback modes are enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 48 ...

Page 61

... C L w/w L (pF max.) (µH max.) 35 0.80 is the inter-winding capacitance, w/w is the leakage inductance, and L PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 0 to 655 foot cable for X-1 Interface .68µ F ±1 0% ,50V 0 .68µ F ±2 0% ,50V 0 .68µ F ±2 0% ,50V DCR pri ...

Page 62

... QDSX. The register set is accessed as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 50 ...

Page 63

... Reserved 08AH 0CAH TOPS Clock Timing Options 08BH 0CBH LCODE Transmit Line Code Configuration 08CH 0CCH Reserved 08DH 0CDH Reserved 08EH 0CEH Reserved 08FH 0CFH Reserved 090H 0D0H CDRC Configuration 091H 0D1H CDRC Interrupt Enable PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 51 ...

Page 64

... PRSG Configuration 0A8H 0E8H PRSM Reserved 0A9H 0E9H PRSM Control/Status 0AAH 0EAH PRSM Bit Error Event Count (LSB) 0ABH 0EBH PRSM Bit Error Event Count (MSB) 0ACH 0ECH XPLS Line Length Configuration 0ADH 0EDH XPLS Control/Status PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 52 ...

Page 65

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Register # 0AEH 0EEH XPLS CODE Indirect Address 0AFH 0EFH XPLS CODE Indirect Data 0B0H 0F0H RSLC Configuration 0B1H 0F1H RSLC Interrupt Enable/Status Reserved for Test PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 53 ...

Page 66

... To ensure that the QDSX operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 54 ...

Page 67

... CDRC Configuration register (010H, 050H, 090H, and 0D0H) takes precedence over the RDUAL bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RDPINV 0 RDNINV 0 RDUAL 0 RRISE 0 AUTO_LLB_EN 0 AUTO_AIS_EN 0 BPVCNT 0 CEPT 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 55 ...

Page 68

... The CEPT bit configures the receiver for E1 applications. When CEPT is set to logic 1, the receiver is configured for E1 applications. When CEPT is set to logic 0, the receiver is configured for T1 applications. All CEPT bits in all four PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 56 ...

Page 69

... PMC-950857 quadrants and in both the Transmit Configuration (registers 001H, 041H, 081H, and 0C1H) and Receive Configuration registers should be set to the same value. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 57 ...

Page 70

... TFALL is set to logic 0, the interface is enabled to sample the inputs on the rising TCLKI[X] edge. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X TDPINV 0 TDNINV 0 TDUAL 0 TFALL 0 CEPT 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 58 ...

Page 71

... Transmit Configuration and Receive Configuration (registers 000H, 040H, 080H, and 0C0H) registers should be set to the same value. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 59 ...

Page 72

... PRBS sequence to the RDD[X] output. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X PRSMTX 0 PRSGTX 1 IBCDTX 0 XIBCTX 1 DJATTX 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 60 ...

Page 73

... TCLKI[X], and line loopback cannot be used. Refer to the operations section for more details on using the QDSX without the DJAT enabled in the transmit path. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 61 ...

Page 74

... Reading these registers does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RLSC 0 XPLS 0 IBCD 0 PRSM 0 LCV_PMON 0 Unused X CDRC 0 DJAT 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 62 ...

Page 75

... QDSX unless DJAT is enabled in the transmit path. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCVINS 0 Unused X AUTO_LLB X RXAISEN 0 TXAISEN 0 DIALB 0 DMLB 0 LINELB 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 63 ...

Page 76

... When LINELB is set to logic 1, the line loopback mode is enabled. When LINELB is set to logic 0, line loopback mode is disabled. Line loopback should not be enabled in the QDSX unless DJAT is enabled in the transmit path. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 64 ...

Page 77

... The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 A_TM[7] X A_TM[6] X PMCTST X DBCTRL X IOTST 0 HIZDATA X HIZIO 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 65 ...

Page 78

... While the HIZDATA bit is a logic one, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 66 ...

Page 79

... The chip identification TYPE bit is set at a logic 0. ID[4:0]: The ID[4:0] bits allows software to identify the version level of the device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RESET 0 TIP X TYPE 0 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 67 ...

Page 80

... The INT[X] bit will be high if the xth QDSX interface causes the INTB pin to transition low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default INT[4] 0 INT[3] 0 INT[2] 0 INT[1] 0 Unused X Unused X Unused X Unused X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 68 ...

Page 81

... The XSEL[1:0] bits configures the QDSX for the desired XCLK input and for the CLKO8X/CLK01X output according to the following table: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default TCLKIA[4] X TCLKIA[3] X TCLKIA[2] X TCLKIA[1] X XCLKA X CLKO8XA X XSEL[1] 0 XSEL[0] 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 69 ...

Page 82

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 XCLK Requirements 24X input clock 24X input clock 8X input clock Reserved PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE CLKO8X/CLK01X Output DJAT smoothed 8X output clock XCLK ÷ 3 XCLK ÷ 8 (CLKO1X) ...

Page 83

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X FIFOBYP 0 PLLREF[1] 0 PLLREF[0] 0 Transmit Reference Source TCLKI[X] input. Clock recovered from the RXTIP[X] and RXRING[X] inputs. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 71 ...

Page 84

... lock 24 x referen ce clo jitter atte nu ation ÷ "H igh -spe ed " clock XSE L [1:0 ] PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE TTX XPL S d ata XPL clo ...

Page 85

... TDUAL input pin is set to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X AMI 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 73 ...

Page 86

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default AMI 0 LOS[1] 0 LOS[0] 0 DCR 0 Reserved 0 ALGSEL 0 O162 0 Reserved 0 Threshold (bit periods) 10 (E1 format selected) 15 (DSX-1 format or AMI line code selected 175 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 74 ...

Page 87

... If O162 is a logic 1, a line code violation is indicated by a LCV output pulse if a bipolar violation is of the same polarity as the last bipolar violation, as per Recommendation O.162. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 75 ...

Page 88

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCVE 0 LOSE 0 LCSDE 0 EXZE 0 Unused X Unused X Unused X Unused X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 76 ...

Page 89

... In the CDRC, excess zeros is defined as a string greater than: 3 consecutive zeros for E1 data consecutive zeros for T1 data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCVI X LOSI X LCSDI X EXZI X Unused X Unused X Unused X LOS X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 77 ...

Page 90

... A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 INT X OVR X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 78 ...

Page 91

... LCV_PMON counters and the PRSM counters. The transfer in progress (TIP) bit in register 007H is polled to determine when the transfer is complete. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 79 ...

Page 92

... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LCV[7] X LCV[6] X LCV[5] X LCV[4] X LCV[3] X LCV[2] X LCV[1] X LCV[0] X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 80 ...

Page 93

... T1 AMI) can be disabled by the BPVCNT bit of the Receive Configuration register (000H, 040H, 080H, and 0C0H). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X LCV[12] X LCV[11] X LCV[10] X LCV[9] X LCV[8] X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 81 ...

Page 94

... FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI X UNDI X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 82 ...

Page 95

... Writing to this register will reset the PLL and, if the SYNC bit in the DJAT Configuration register is high, will also reset the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 83 ...

Page 96

... Writing to this register will reset the PLL and, if the SYNC bit is high, will also reset the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 84 ...

Page 97

... EMPTY or FULL alarm conditions. CENT can only be set to logic 1 if SYNC is set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X WIDEN 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 85 ...

Page 98

... This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 1, the PLL jitter attenuation is limited. When LIMIT is set to logic 0, the PLL is allowed to operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 86 ...

Page 99

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Reserved 0 Unused X Unused X Unused X DSEL1 0 DSEL0 0 ASEL1 0 ASEL0 0 ACTIVATE Code ASEL1 ASEL0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE CODE LENGTH 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits 87 ...

Page 100

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default LBACP X LBDCP X LBAE 0 LBDE 0 LBAI X LBDI X LBA X LBD X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 88 ...

Page 101

... A logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 89 ...

Page 102

... Note that bit ACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default ACT7 0 ACT6 0 ACT5 0 ACT4 0 ACT3 0 ACT2 0 ACT1 0 ACT0 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 90 ...

Page 103

... Note that bit DACT7 corresponds to the first code bit received. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default DACT7 0 DACT6 0 DACT5 0 DACT4 0 DACT3 0 DACT2 0 DACT1 0 DACT0 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 91 ...

Page 104

... CL1 CL0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default EN 0 Reserved 0 Unused X Unused X Unused X Unused X CL1 0 CL0 0 Code Length PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 92 ...

Page 105

... Codes bits in length may be accommodated by treating them as half of a double-sized code (i.e. a 3-bit code would use the 6-bit code length setting). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 93 ...

Page 106

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default IBC7 X IBC6 X IBC5 X IBC4 X IBC3 X IBC2 X IBC1 X IBC0 X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 94 ...

Page 107

... PRBSERR 0 and writing it 1 again, or vice versa error successfully inserted. PRBSERR has no effect when PRBSGEN is set to 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X PRBSINV 0 PRBSERR 0 PRBSGEN 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 95 ...

Page 108

... The interrupt is cleared by reading this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default PRBSINV 0 Reserved 0 OOSE 0 OOSI X OOS X INTE 0 INT X OVR X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 96 ...

Page 109

... Alternatively, the PRSM Control/Status register may be polled until the INT bit goes to logic 1, indicating PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 97 ...

Page 110

... PRSM counters as well as the LCV_PMON registers of all four quadrants. The transfer in progress (TIP) bit in register 007H is polled to determine when the transfer is complete. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 98 ...

Page 111

... Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BER[7] X BER[6] X BER[5] X BER[4] X BER[3] X BER[2] X BER[1] X BER[0] X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 99 ...

Page 112

... PMON’s holding register addresses register 007H. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default BER[15] X BER[14] X BER[13] X BER[12] X BER[11] X BER[10] X BER[9] X BER[8] X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 100 ...

Page 113

... Reserved The reserved bits must be programmed to logic 0 for correct operation. ILS[2:0]: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default RPT 0 Reserved 0 Reserved X Reserved X Reserved X Reserved 0 Reserved 0 Reserved 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 101 ...

Page 114

... Performance Monitor (DPM) alarm signal. This bit is cleared when the register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X TAIS 0 DPMV X DPMI X DPME 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 102 ...

Page 115

... When DPME is set to logic 0, detection of a driver performance monitor alarm condition is disabled from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 103 ...

Page 116

... CRA1 0 CRA0 0 CRA0 Internal Code Register 0 CODE register #0 - first code applied 1 CODE register #1 0 CODE register #2 1 CODE register #3 0 CODE register #4 1 CODE register #5 0 CODE register #6 1 CODE register #7 - last code applied PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 104 ...

Page 117

... DATA SHEET PMC-950857 See the Operations section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 105 ...

Page 118

... See the Operations section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X CRD3 0 CRD2 0 CRD1 0 CRD0 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 106 ...

Page 119

... The THS bit is internally ORed with the CEPT bit in the Receive Configuration Register (Registers 000H, 040H, 080H, 0C0H). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X THS 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 107 ...

Page 120

... When the QDSX is reset, the SQE bit is set to logic 0, disabling a squelch event from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused SQI X SQE 0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 108 ...

Page 121

... Normal Mode Registers Master Test Register QDSX Test Reserved CDRC Test Register 0 CDRC Test Register 1 CDRC Test Register 2 QDSX Test Reserved LCV_PMON Test Register 0 LCV_PMON Test Register 1 LCV_PMON Test Reserved DJAT Test Register 0 DJAT Test Register 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 109 ...

Page 122

... IBCD Test Register 0 IBCD Test Register 1 IBCD Test Reserved XIBC Test Register 0 XIBC Test Register 1 QDSX Test Reserved XPLS Test Register 0 XPLS Test Register 1 XPLS Test Register 2 XPLS Test Register 3 RSLC Test Register 0 RSLC Test Register 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 110 ...

Page 123

... ISSUE 5 Bit 5 Bit 4 Bit 3 DCR TCLKI[1] XCLK TCLKI[2] XCLK TCLKI[3] XCLK TCLKI[4] XCLK Bit 5 Bit 4 Bit 3 1 CLKO8X 1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Bit 2 Bit 1 Bit 0 TDN[1] TDP[1] RDUAL TDUAL TDN[2] TDP[2] TDN[3] TDP[3] TDN[4] TDP[4] Bit 2 Bit 1 Bit 0 RCLKO[1] ...

Page 124

... EXTEST IDCODE SAMPLE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Bit 5 Bit 4 Bit Selected Register Boundary Scan Identification Boundary Scan PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Bit 2 Bit 1 Bit 0 RCLKO[3] 1 INT 1 INT 1 INT 1 RDP[3] ...

Page 125

... Bypass Boundary Scan Pin/Enable Register Bit 63 RDP[3] 62 RCLKO[2] 61 RDN[2] 60 RDP[2] 59 RCLKO[ RDN[1] 49 RDP[1] 48 RDUAL 47 INTB 46 INTB_OEN 45 D[0] PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Instruction Codes, IR[2:0] 011 100 101 110 111 Boundary Scan Register Bit 113 ...

Page 126

... D0_OEN 43 D[1] 42 D1_OEN 41 D[2] 40 D2_OEN 39 D[3] 38 D3_OEN 37 D[4] 36 D4_OEN 35 D[5] 34 D5_OEN 33 D[6] 32 D6_OEN 31 D[7] 30 D7_OEN 29 HIZ[2] 28 HIZ[4] PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Boundary Scan Register Bit 114 ...

Page 127

... The pulse is produced differentially across the transformer primary PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Typical CODE Output 0.05 V 1000 Voltage 0.31 V 1001 0.58 V 1010 0.85 V 1011 1.16 V 1100 1.38 V 1101 1.65 V 1110 1.91 V 1111 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE as follows: Typical Output Voltage 2.16 V 2.43 V 2.70 V 2.97 V 3.23 V 3.49 V 3.76 V 4.02 V 115 ...

Page 128

... PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE at half the bit rate 116 ...

Page 129

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Recommended Code Register Values (WIDEN= PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 117 ...

Page 130

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 118 ...

Page 131

... Write the CODE register address (0-7) in the XPLS CODE Indirect Address register (register 02EH, 06EH, 0AEH, 0EEH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 119 ...

Page 132

... DPLL to lock onto. In this application, the N1 and N2 divisors should be changed to C0H (i.e. divisors of 193 for T1 applications) or FFH (i.e. divisors of 256 for E1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 120 ...

Page 133

... XPLS with its required clocks. The possible cases are: a) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 where N2= PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE corner frequency TCLKI[X] average = frequency value in the Output Clock Divisor Control register 121 ...

Page 134

... FIFO not in Tx path, XSEL[ XSEL[ This setting is reserved. 12.3.5 FIFO path, XSEL[ XSEL[ This setting is reserved. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 122 ...

Page 135

... TRSTB TCK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Boundary Scan Register Device Identification Register Bypass Register Instruction Register and Decode Control Select Tri-state Enable PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Mux DFF TDO 123 ...

Page 136

... The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary TMS. The finite state machine is shown in Figure 21. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 124 ...

Page 137

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 1 Select-DR-Scan 0 1 Capture-DR 0 Shift- Exit1-DR 0 Pause- Exit2-DR 1 Update- All transitions dependent on input TMS PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 1 Select-IR-Scan 0 1 Capture-IR 0 Shift- Exit1-IR 0 Pause- Exit2-IR 1 Update- 125 ...

Page 138

... The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 126 ...

Page 139

... Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 127 ...

Page 140

... RDP[3] IN_CELL 0 RCLKO[2] IN_CELL 0 RDN[2] IN_CELL 0 RDP[2] IN_CELL 0 RCLKO[1] IN_CELL 100001100 RDN[1] IN_CELL 0 RDP[1] IN_CELL 1 RDUAL IN_CELL 0 INTB IN_CELL 1 INTB_OEN 1 IN_CELL 0 D[0] PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Register Cell Type I.D. Bit Bit 27 OUT_CELL - 26 OUT_CELL - 25 OUT_CELL - 24 OUT_CELL - 23 OUT_CELL - 22 OUT_CELL - 21 OUT_CELL - 20 IN_CELL - 19 IO_CELL ...

Page 141

... IN_CELL 1 D[3] D3_OEN 1 IN_CELL 1 IN_CELL 0 D[4] D4_OEN 1 IN_CELL 0 IN_CELL 1 D[5] D5_OEN 1 IN_CELL 1 OUT_CELL 0 D[6] D6_OEN 1 OUT_CELL 1 OUT_CELL - D[7] D7_OEN 1 OUT_CELL - HIZ[2] 2 OUT_CELL - HIZ[4] 3 OUT_CELL - PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Register Cell Type I.D. Bit Bit 16 OUT_CELL - 15 IO_CELL 14 OUT_CELL - 13 IO_CELL - 12 OUT_CELL - 11 IO_CELL - 10 OUT_CELL - 9 IO_CELL - 8 OUT_CELL - 7 IO_CELL - 6 OUT_CELL ...

Page 142

... G1 and G2. The ID Code bit is as listed in the table above. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE MUX PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Scan Chain Out INPUT to internal logic 130 ...

Page 143

... UPDAT can Chain In PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE MUX MUX PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE S can Chain Out OUT PUT or Enable D C 131 ...

Page 144

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Scan Chain Out MUX Scan Chain Out OUT_CELL IO_CELL Scan Chain In PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE INPUT to internal logic G1 1 OUTPUT MUX 1 to pin D C I/O PAD 132 ...

Page 145

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE continuous zeros continuous zeros CVINS = 1 caus es omis s ion of firs t bipolar violation puls e. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 133 ...

Page 146

... ISSUE 5 continuous zeros continuous zeros CVINS = 1 caus es omis s ion of bipolar puls e and violat ion of s ame polarit y as previous violat ion. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 134 ...

Page 147

... To generate another line code violation, the LCVINS bit must be reset to logic 0 and then set to logic 1 again. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE CVINS = 1 caus es a bipolar violat ion. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 135 ...

Page 148

... Latch-Up Current (T +85°C) Package Power Dissipation PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 -55°C to +125°C -65°C to +150°C -0.6V to +6.0V -0.6V to VDD+0.6V ±1000 V = -40°C to ±100 mA A 2.0 W PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 136 ...

Page 149

... Bidirectional Capacitance PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Typ Units PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Conditions T = 25° MHz A (sampled only 25° MHz A (sampled only 25° MHz ...

Page 150

... Min Typ. Max 5.0 5.25 -0.5 0.8 2 -0.6 +0.6 0.1 0.4 VDD- 4.7 1.0V 3.5 1.0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Units Conditions Volts Volts Guaranteed Input LOW Voltage + Volts Guaranteed DD Input HIGH Voltage Volts VD Volts for Data Bus Pins and -2 mA for others, Note 3 ...

Page 151

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Min Typ. Max 1.0 +20 +83 +200 -10 0 +10 -10 0 +10 -10 0 +10 325 330 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Units Conditions Volts µ GND, Notes 1, 3 µ Notes µ GND, Notes 2, 3 µ Notes DD ...

Page 152

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 resistor is connected across TXTIP and TXRING line reflected back through a PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE template, and a 44 140 ...

Page 153

... Propagation Delay tZ Valid Read Negated to Output RD Tristate tZ Valid Read Negated to INTB open INTH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE ±5% DD PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units ...

Page 154

... A valid read cycle is defined as a logical OR of the CSB and the RDB signals. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE Valid Address ALR PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE tH AR ALR INTH tZ RD Valid Data 142 ...

Page 155

... Data to Valid Write Hold Time DW tH Address to Valid Write Hold Time AW tV Valid Write Pulse Width WR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units ...

Page 156

... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Valid Address tS tH ALW Valid Data is not applicable if address latching is used. PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ALW 144 ...

Page 157

... MHz for T1, 49.152 MHz for E1) Figure 31 - XCLK Input Timing for Jitter Attenuation XCLK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 =5V ±5% DD 1/t XCLK PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 50 MHz 145 ...

Page 158

... TCLKI to TDD/TDP or TDN Input Hold-up Time Figure 32 - TCLKI Input Timing TCLKI[x] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE TTCLKI TTCLKI ETCLKI PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 1.545 MHz 1 2.049 MHz 165 ns 165 ns ...

Page 159

... DATA SHEET PMC-950857 TDD/TDP[x], TDD/TDP[x], PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 Valid TDN[x] t STCLKI TCLKI[x] With TFALL bit =1 Valid TDN[x] t STCLKI TCLKI[x] With TFALL bit =0 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE t HTCLKI t HTCLKI 147 ...

Page 160

... XSEL[1:0] is not set to 10 binary. Figure 33 - CLKO8X Input Timing Diagram (FIFO not in TX path) CLKO8X TCLKI[x] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE CLKO8X CLKO8X PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 148 ...

Page 161

... XSEL[1:0] is set to 10 binary. Figure 34 - XCLK Input Timing Diagram (FIFO not in TX path) XCLK TCLKI[x] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE XCLK XCLK PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 149 ...

Page 162

... RCLKO[x] RDD/RDP[x], RLCV/RDN[x] RCLKO[x] RDD/RDP[x], RLCV/RDN[x], PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 t PRCLKO With RRISE bit=0 t PRCLKO With RRISE bit=1 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 50 ns Valid Valid 150 ...

Page 163

... TMS Hold time to TCK tS TDI TDI Set-up time to TCK tH TDI TDI Hold time to TCK t P TDO TCK Low to TDO Valid PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 1 MHz 40 60 ...

Page 164

... DATA SHEET PMC-950857 Figure 36 - JTAG Port Interface Timing TCK TMS TDI TCK TDO PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE TMS TMS tS tH TDI TDI tP TDO PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 152 ...

Page 165

... Volt point of the clock to the 1.4 Volt point of the input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE AIN PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE Min Max. Units 200 300 ns 250 ...

Page 166

... Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 7. Maximum output propagation delays are measured with load on the outputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 154 ...

Page 167

... ORDERING AND THERMAL INFORMATION Table 26 - QDSX Ordering Information PART NO. PM4314-RI Table 27 - QDSX Thermal Information PART NO. PM4314-RI PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 DESCRIPTION 128 Plastic Quad Flat Pack (PQFP) CASE TEMPERATURE -40°C to 85°C PM4314 QDSX ...

Page 168

... DETAIL A 128 PIN METRIC RECTANGULAR PLASTIC QUAD FLATPACK-MQFP 22.95 0.25 2.57 19.90 16.95 20.00 2.70 23.20 17.20 0.53 2.87 23.45 20.10 17.45 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE A A2 NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE. C ccc ccc E1 L 13.90 0.73 0.17 0.88 14 ...

Page 169

... DATA SHEET PMC-950857 NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE 157 ...

Page 170

... PMC-Sierra, Inc. has been advised of the possibility of such damage. © 1998 PMC-Sierra, Inc. PMC-950857 (R5) ref PMC-950739 (R4) Issue date: June 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 5 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com PM4314 QDSX QUAD T1/E1 LINE INTERFACE DEVICE ...

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