PM7350-PI PMC-Sierra Inc, PM7350-PI Datasheet
PM7350-PI
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PM7350-PI Summary of contents
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... RELEASED DATA SHEET PMC-1980581 DUAL SERIAL LINK, PHY MULTIPLEXER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 TM S/UNI - DUPLEX S/UNI DUPLEX DATA SHEET RELEASED ISSUE8: DECEMBER 2005 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ...
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... U.S. Patent No. 6,104,277 U.K. Patent No. 2,305,541 Canadian Patent No. 2,179,246 French Patent No. 2,738,953 Relevant patent applications and other patents may also PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER exist. ...
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... RELEASED DATA SHEET PMC-1980581 Contacting PMC-Sierra PMC-Sierra 100-2700 Production Way Burnaby, BC Canada V5A 4X1 Tel: (604) 415-6000 Fax: (604) 415-6200 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ...
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... Updated list of patents. Added references: 9. PMC-Sierra; Using External Pull-Down Resistors with 5V Tolerant 3.3V Inputs, PMC-2012282. 10. PMC-Sierra; PM7350 S/UNI-DUPLEX Device Errata, PMC-1990883. Added sentence "All address pins are latched." to ALE pin description. Updated Table 8 and Table 9. Appended additional “Notes on Pin Descriptions” ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Updated to incorporate Revision B changes outinled in previous Errata. Change bars highlight specific changes. Changed confidentiality notices for document’s public release. Extensive updates throughout First release PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ...
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... REGISTER MEMORY MAP .........................................................82 10 NORMAL MODE REGISTER DESCRIPTION ........................................86 11 TEST FEATURES DESCRIPTION........................................................172 11.1 RAM BUILT-IN-SELF-TEST .......................................................175 11.2 JTAG TEST PORT .....................................................................179 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER i ...
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... D.C. CHARACTERISTICS....................................................................213 16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................................................................217 17 A.C. TIMING CHARACTERISTICS.......................................................221 18 ORDERING AND THERMAL INFORMATION.......................................228 19 MECHANICAL INFORMATION.............................................................230 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ii ...
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... REGISTER 0X13: INPUT CELL AVAILABLE ENABLE (MSB)......................... 112 REGISTER 0X14: SCI-PHY/ANY-PHY OUTPUT CONFIGURATION.............. 114 REGISTER 0X15: SCI-PHY/ANY-PHY OUTPUT POLLING RANGE .............. 117 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER iii ...
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... REGISTER 0X34: RXD2 EXTRACT FIFO CONTROL ....................................135 REGISTER 0X35: RXD2 EXTRACT FIFO INTERRUPT STATUS...................136 REGISTER 0X3C: RECEIVE LOGICAL CHANNEL FIFO CONTROL.............137 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER iv ...
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... REGISTER 0X62: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (LSB).....................................................................................................157 REGISTER 0X63: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER........157 REGISTER 0X64: TRANSMIT HIGH-SPEED SERIAL CELL COUNTER (MSB)....................................................................................................158 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER v ...
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... REGISTER 0X71:TRANSMIT SERIAL INDIRECT CHANNEL DATA ..............169 REGISTER 0X74:TRANSMIT SERIAL ALIGNMENT CONTROL ....................171 REGISTER 0X80: MASTER TEST ..................................................................173 REGISTER 0X83: MISCELLANEOUS TEST ..................................................174 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER vi ...
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... TIMING ..............................................................................................205 FIG. 19 SCI-PHY INTERFACE, INPUT BUS MASTER TRANSFER TIMING ..............................................................................................206 FIG. 20 ANY-PHY INTERFACE, INPUT BUS SLAVE TRANSFER TIMING ..............................................................................................207 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER vii ...
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... FIG. 31: INGRESS SCI-PHY/ANY-PHY INTERFACE TIMING ........................222 FIG. 32: EGRESS SCI-PHY/ANY-PHY INTERFACE TIMING..........................223 FIG. 33: CLOCKED SERIAL DATA INTERFACE .............................................224 FIG. 34: JTAG PORT INTERFACE TIMING.....................................................226 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER viii ...
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... TABLE 13 SCI-PHY/UTOPIA AND ANY-PHY COMPARISON, EGRESS DIRECTION .........................................................................................56 TABLE 14 EIGHT BIT ANY-PHY BUS SLAVE, OUTPUT CONFIGURATION ...............................................................................57 TABLE 15 SIXTEEN BIT ANY-PHY BUS SLAVE, OUTPUT CONFIGURATION ...............................................................................57 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ix ...
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... TABLE 23 LVDS LINK 59 BYTE CELL CONFIGURATIONS WITH CRC ........194 TABLE 24 OUTSIDE PLANT THERMAL INFORMATION..............................228 TABLE 25 THERMAL RESISTANCE VS. AIR FLOW TABLE 26 DEVICE COMPACT MODEL PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 4 .......................................................228 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 3 ...................................228 x ...
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... Interworks with PM7351 S/UNI-VORTEX devices to implement a point-to- multipoint serial backplane architecture, with optional 1:1 protection of the common card. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 1 ...
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... Standard 5 pin P1149.1 JTAG test port. • Low-power, 3.3V CMOS technology. • 160-pin high-performance plastic ball grid array (PBGA) package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 2 ...
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... Multiservice access multiplexer. • Universal Mobile Telecommunication System (UMTS) wireless base stations. • 16 channel cell delineation (I.432 transmission convergence processing). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 3 ...
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... Test Method for Junction-to-Case Thermal Resistance Measurements of Ceramic Packages. 1988. 9. PMC-Sierra; “Using External Pull-Down Resistors with 5V Tolerant 3.3V Inputs”, PMC-2012282. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 4 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Policing Buffering S/UNI- OA&M Discard VORTEX Scheduling WAN Card Policing Buffering S/UNI- OA&M Discard VORTEX Scheduling WAN Card PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER WAN OA&M up-link WAN OA&M up-link 5 ...
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... Component costs are reduced, while system reliability increases due to reduced component count. In this type of architecture there are often three stages of signal concentration or multiplexing, as shown in Fig 2. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 6 ...
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... If the active core card (or its LVDS link) should fail, protection switching PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 S/UNI- VORTEX Policing Buffering OA&M Discard S/UNI- Scheduling VORTEX PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER WAN OA&M up-link WAN Card 7 ...
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... Either Utopia mode or clock and data mode can be selected, but not both at once. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Line Card Rx Clock Rx Data Tx Clock S/UNI- DUPLEX Tx Data PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER this mode, 4-wire LVDS 8 ...
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... Off card or off shelf bus extension. 5. Cell delineation (I.432 processing). 6. Protection switching. Examples of these types of configurations are shown in Fig. 4 and Fig. 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 9 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 S/UNI- LVDS DUPLEX 16 bit bus LVDS S/UNI- DUPLEX LVDS S/UNI- S/UNI- DUPLEX Clock + data PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Bus master Bus slave Bus master 8/16 bit bus 10 ...
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... S/UNI- DUPLEX master S/UNI- Bus master DUPLEX Example of protection switching between cards PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 S/UNI- DUPLEX S/UNI- DUPLEX PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Bus slave Bus slave 11 ...
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... Although separated to improve clarity, many signals in the following diagram share physical package pins. The use of the SCI-PHY/Any-PHY interfaces and the clocked serial data interfaces is mutually exclusive. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 12 ...
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... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 per-PHY buffers AT M per-PHY buffers 2 Cell Buffer 4 Cell FIFO to all blocks PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER RXD1+ RXD1- TXD 1+ TXD 1- Cell Processor RXD2+ RXD2- TXD 2+ TXD 2- Clock ...
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... DATA SHEET PMC-1980581 6 DESCRIPTION The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-VORTEX, to implement a point-to-point serial backplane interconnect architecture. The primary role of the S/UNI-DUPLEX is to interface devices (typically framers or PHYs) and transfer 52-56 byte data cells in serial format to/from a backplane. Devices interface to the S/UNI-DUPLEX via 16-bit SCI-PHY/Utopia/Any-PHY bus, or optionally via a 16 port clock and data interface ...
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... Provides read/write access to all configuration and status registers. • Provides CRC32 calculation and cell transfer registers to support an embedded microprocessor to microprocessor communication channel over the LVDS link. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 15 ...
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... LRXD[1] OADDR[2] OADDR[4] ODAT[1] ODAT[3] OCA LRXC[2] LTXC[0] LRXC[1] LRXC[4] LRXD[5] OENB ODAT[0] VSS OSX LRXC[3] VDD LRXD[2] LTXC[2] BOTTOM VIEW PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER IADDR[3] IADDR[1] ICA RSTOB LRXC[15] LRXD[14] LRXC[13] IENB IPRTY IDAT[15] VSS VDD ...
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... LVDS output signal levels. L14 The Analog Test Points (ATP) are provided for L13 production test purposes. In mission mode they are high impedance and should be connected to ground. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 17 ...
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... If the active link is changed, RCLK can not be guaranteed to be glitch free. Because of these two factors, RCLK must be cleaned PLL before it is suitable for use as a timing reference. Clocked Data Serial Interface PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 18 ...
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... LRXD[n] can be clocked either by the rising or J2 falling edge of the corresponding LRXC[n] input, K3 depending on the value of the LRXCINV bit of the L2 Master Configuration register. By default, the rising P2 edge is used. M4 These inputs are only active if the SCIANY input logic low L10 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 19 ...
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... By default, the rising edge is used. J1 These outputs are only active if the SCIANY input logic low When SCIANY is logic high, LTXD[3] and LTXD[0] M11 become inputs and need to be tied to VDD or VSS N12 through a pull pull down. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 20 ...
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... Any-PHY specification. The Any-PHY protocol is supported only when the input port cell interface is configured as a bus slave (IMASTER input must be set to logic 0 if IANYPHY is high). IANYPHY is an asynchronous input and is expected to be held static. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 21 ...
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... S/UNI-DUPLEX upstream cell buffer. IFCLK must cycle MHz or lower instantaneous rate. All SCI-PHY/Any-PHY input port timing is relative to the rising edge of IFCLK. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 22 ...
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... IDAT[15:0] stream. ISX must be asserted for each cell. An interrupt may be generated if ISX is high during any word other than the expected first word of the cell structure. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 23 ...
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... ISX being asserted high Any-PHY bus slave (IMASTER = 0, IANYPHY = 1) IPRTY is not considered valid when autonomous deselection occurs after the last word of a cell. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 24 ...
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... Therefore, the master should refrain from polling that logical channel in the interim. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 25 ...
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... IADDR[4:0] is outside the address range specified by ICAEN[31:0] of the Input Cell Available Enable registers. ICA is sampled or updated on the rising edge of IFCLK. This signal is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 26 ...
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... ISX) even if IENB is left asserted SCI- PHY/Utopia slave ISX is not defined subsequent cell is transferred (provided one is available) if IENB is held low beyond the end of a cell. This signal is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 27 ...
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... Polling occurs when IAVALID is sampled low and the S/UNI-DUPLEX drives ICA with the cell buffer availability status of the logical channel indexed by IADDR[4:0]. There is a one IFCLK cycle gap between IAVALID sampled low and ICA. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 28 ...
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... The S/UNI-DUPLEX supports polling in contiguous cycles if IAVALID is held active. ICA is delayed by an additional IFCLK cycle.IAVALID is sampled or updated on the rising edge of IFCLK. This signal is only active if the SCIANY input is a logic high. Parallel Bus - Output PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 29 ...
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... PHY/Utopia or the Any-PHY receive protocol depending on the state of the OANYPHY input. The OADDR[4:0], OAVALID, OENB signals are inputs. The OCA signal is an output. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 30 ...
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... PHY devices. OFCLK must cycle MHz or lower instantaneous rate, but a high enough rate to avoid a FIFO overflow. All SCI- PHY/Any-PHY output port timing is relative to the rising edge of OFCLK. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 31 ...
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... OENB assertion.. When OANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting OSOC high-impedance until reselection. This output is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 32 ...
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... S/UNI-VORTEX device is not selected for transfer. When OANYPHY is high, autonomous deselection occurs after the last word of a cell resulting in setting OSX high-impedance until reselection. This input is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 33 ...
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... ODAT[15:0] bus is high impedance. Autonomous deselection occurs after the last word of a cell resulting in setting ODAT[15:0] high- impedance until reselection. These outputs are only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 34 ...
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... OPRTY is high impedance Any-PHY bus slave autonomous deselection occurs after the last word of a cell resulting in setting OPRTY high-impedance until reselection. This output is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 35 ...
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... When OAVALID is sampled low, OCA becomes high impedance. OCA is delayed by an additional clock cycle in Any-PHY configuration. OCA is sampled or updated on the rising edge of OFCLK. This signal is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 36 ...
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... S/UNI-DUPLEX is reselected (via OSX) even if OENB is left asserted SCI- PHY/Utopia slave OSX is not defined subsequent cell is transferred (provided one is available) if OENB is held low beyond the end of a cell. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 37 ...
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... When OENB is sampled high or the S/UNI-DUPLEX is not selected, no read is performed and outputs ODAT[15:0], OPRTY, OSX and OSOC become high impedance. OENB is sampled or updated on the rising edge of OFCLK. This signal is only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 38 ...
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... OANYPHY = 0) the device must be reselected to resume a cell transferred that has been halted by deasserting OENB high. The OADDR[4:0] bus is sampled or updated on the rising edge of OFCLK. These signals are only active if the SCIANY input is a logic high. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 39 ...
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... Note that when not being used, CSB must be tied high. If CSB is not required (i.e., registers accesses are controlled using the RDB and WRB signals only), CSB must be connected to an inverted version of the RSTB input. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 40 ...
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... A[5:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-DUPLEX to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor. All address pins are latched. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 41 ...
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... The test data output (TDO) signal carries test data out of the S/UNI-DUPLEX via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is inactive except when scanning of data is in progress. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 42 ...
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... ESD protection devices. When tied to +3.3V, the inputs and bi-directional inputs will only tolerate 3.3V level inputs. B3 The digital power (VDD) pins should be connected well-decoupled +3 supply. C13 D10 E2 E14 M12 N3 N13 P6 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 43 ...
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... L12 The ground (CAVS) pin for the analog clock synthesis unit. This pin should be connected to analog GND. It should be electrically isolated (as much as possible) from the other ground connections. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 44 ...
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... G7 The Thermal Vias (GND) are used to improve G8 thermal conductance of the device package. They H7 should be connected to the PCB ground plane. The H8 GND pins are not electrically connected to the other ground pins of the package. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 45 ...
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... For CAVD (Analog Power network consisting ohm resistor and electrolytic/tantalum capacitor is recommended 0.001 uF ceramic capacitor connected in parallel with the 1 uF capacitor is also suggested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 46 ...
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... IANYPHY and OANYPHY inputs are tied high, SCI-PHY or Utopia is selected when the inputs are tied low. Input and output bus PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 47 ...
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... TxEnb* RWRENB TxAddr[4:0] RADDR[4:0] n/a RAVALID TxData[15:0] RDAT[15:0] TxPrty RPRTY TxClav RCA TxSOC RSOC n/a n/a PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER SCI-PHY Any-PHY Bus Level 2 Slave Bus Master RFCLK TCLK RWRENB TENB RADDR[4:0] TADR[4:0] RAVALID TADR[5] RDAT[15:0] TDAT[15:0] ...
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... Fig. 6) are described in Table 2. 16 bit bus options (shown in Fig. 7) are described in Table 3. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 49 ...
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... H1- user bytes then H1-H4 user bytes then H1-H5. Register 0x0C H5UDF PRELEN 0 00 Short cell, no H5/UDF field 1 00 Default, Utopia compatible user word then H1- user word, H1-H4, then H5/UDF PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes Notes 50 ...
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... H1-H4, no PHY user bytes, H1-H4, H5/UDF, no PHY ID PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes Short cell, no PHY ID is generated Default setting. Utopia compatible, standard 53 byte cell, no PHY ID 1 user byte, H1-H4, no PHY ID 1 user byte, H1-H5, no PHY ID ...
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... H1- user bytes then H1- user bytes then H1-H5 Register 0x0C H5UDF PRELEN 0 00 H1-H4, no H5/UDF field 1 00 Default, Utopia compatible user word then H1- user word, H1-H4, then H5/UDF PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes Notes 52 ...
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... PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes PHY ID in Word 0, H1-H4 only Default setting. PHY ID in Word 0, H1-H5 PHY ID in Word 0, 1 user byte, H1- H4 PHY ID in Word 0, 1 user byte, H1- H5 PHY ID in Word 0, 2 user bytes, H1- ...
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... PHY ID in Word 0, 2 user bytes, H1- PHY ID in Word 0, 2 user bytes, H1-H4, H5/UDF Most common setting when Utopia compatibility is desired. Standard 54 byte cell, PHY ID embedded in H5/UDF user bytes, H1-H4, PHY ID in H5/UDF PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes 54 ...
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... PHY ID, 2 user bytes then H1- PHY ID, 2 user bytes then H1-H5 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Any-PHY ICA is driven or becomes high impedance on the IFCLK rising edge following the one that samples a IAVALID low or high respectively. An extra word (Word 0) is prepended to the cell coincident with the assertion of the ISX signal ...
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... PHY ID, user word, then H1-H4, no H5/UDF 1 01 PHY ID, user word, H1-H4, then H5/UDF SCI-PHY/Utopia PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Notes Any-PHY 0DAT[15:0], 0PRTY, 0SOC and OSX are driven or become high impedance on the OFCLK rising edge following the one that samples OENB low or high, respectively ...
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... PHY user bytes, H1- PHY user bytes, H1-H4, H5/UDF PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER High coincident with the second word of the cell data structure. Permitted by deasserting OENB high. The cell transfer resumes unconditionally when OENB is asserted low again. ...
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... Note 1: Optionally, the H5 field can be overwritten PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Bit 7 Bit 5 Bit 4 Extended PHYID[4:0] Address User Prepend User Prepend PAYLOAD1 PAYLOAD48 by the Extended Address and PHYID[4:0]. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Bit 0 58 ...
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... PMD overhead bit locations. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Extended Address User Prepend PAYLOAD1 PAYLOAD3 PAYLOAD47 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Bit 5 Bit 4 Bit 0 PHYID[4: UDF PAYLOAD2 PAYLOAD4 PAYLOAD48 59 ...
Page 75
... ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Fig. 8. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 60 ...
Page 76
... In this case, the serial data is segmented into 53 byte packets independent of the contents, and then transported across the high-speed LVDS links. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 61 ...
Page 77
... FIFOs from emptying, else the clear channel data will be interrupted by an automatically generated ATM idle cell pattern. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 62 ...
Page 78
... Failure to establish cell alignment results in a loss of cell delineation (LCD) alarm. The entire bit stream is scrambled with a x scrambler.Table 16 summarizes the contents of the system prepended bytes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER self-synchronous 63 ...
Page 79
... The state of the CA select bit determines which half of the PHY devices the CA[15:0] bits correspond to. CASEL toggles with each cell transmitted. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ATM Payload ATM Payload 48 bytes 64 ...
Page 80
... The remaining codes are either reserved or user defined. The receiver ensures the pattern is the same for 10 (default repetitions before validating a PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 65 ...
Page 81
... The TREF[5:0] binary value represents the number of high-speed link bytes after this one at which the timing reference is inferred. An all ones value indicates no timing mark is associated with this cell. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 66 ...
Page 82
... The loopbacks can be enabled individually or simultaneously, and each link can be looped back independently of the other. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 67 ...
Page 83
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 per-PH Y buffers AT M per-PH Y buffers 2 Cell Buffer 4 C ell FIFO to all blocks PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER RXD1+ RXD1- TXD 1+ TXD 1- Cell Processor RXD2+ RXD2- TXD 2+ TXD 2- Clock ...
Page 84
... Serial Links Maintenance register. RDI can be inserted manually on a high- speed serial link by setting the corresponding TXD1 Bit Oriented Code or TXD2 Bit Oriented Code register to all zeros. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ...
Page 85
... RDIDIS1 or RDIDIS2 register bit be set to logic 1, or else a loss-of-signal or loss-of-cell-delineation event would cause a premature loopback due to a pre-emptive Remote Defect Indication (RDI) code being sent. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 70 ...
Page 86
... HUNT or PRESYNC states. The LCD alarm is cleared after 1318 consecutive cells in the SYNC state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Codeword (left bit transmitted first) 11111111 00000000 ...
Page 87
... RXAUTOSEL = 1) the active bit transmitted on the two LVDS links will indicate which link is currently chosen as active. This reflected ACTIVE bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 72 ...
Page 88
... On the inactive link only inter-processor communication cells (hereafter called control cells) are PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 73 ...
Page 89
... In the LVDS transmit direction, the primary task of the S/UNI-DUPLEX is accept cells from the parallel bus, clocked serial interfaces, or microprocessor port PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 74 ...
Page 90
... PHYs are buffered in 16 dedicated logical channel FIFOs. They should be programmed in the Transmit Logical Channel FIFO Depth PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 75 ...
Page 91
... When the S/UNI-VORTEX’s LVDS receiver cell buffer becomes congested the S/UNI-VORTEX will immediately clear the CA bits and possibly the UPCA fields PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 76 ...
Page 92
... The timing signal received on the active RXD1+/- or RXD2+/- inputs is presented on RX8K. Rising edges of TX8K input are encoded in the TXD1+/- and TXD2+/- cells. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 77 ...
Page 93
... The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-DUPLEX identification code is 173500CD hexadecimal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 78 ...
Page 94
... Optional CRC-32 calculation over the last 48 bytes of the cell relieves the microprocessor of this task. The CRC-32 generator polynomial is consistent with AAL5 G( PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER ...
Page 95
... H1-H5 are shown in Fig. 11 there is no restriction on the values they can contain. See Section 12.1.1 for details on the cell write protocol. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 80 ...
Page 96
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Bit 7 Unused Unused * User Prepend * User Prepend UDF Unused Unused PAYLOAD1 PAYLOAD48 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Bit 0 81 ...
Page 97
... Extended Address Match (LSB) 0x07 Extended Address Match (MSB) 0x08 Extended Address Mask (LSB) 0x09 Extended Address Mask (MSB) 0x0A Output Address Match PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 82 ...
Page 98
... RXD1 Extract FIFO Control 0x31 RXD1 Extract FIFO Interrupt Status 0x32 – Reserved 0x33 0x34 RXD2 Extract FIFO Control PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 83 ...
Page 99
... Receive Serial Indirect Channel Configuration 0x6A Receive Serial Indirect Channel Interrupt Enables 0x6B Receive Serial Indirect Channel Interrupt and Status PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 84 ...
Page 100
... Transmit Serial Alignment Control 0x75 – Reserved 0x7F 0x80 – Reserved for test registers 0xFF For all register accesses, CSB must be low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 85 ...
Page 101
... To ensure that the S/UNI-DUPLEX operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 86 ...
Page 102
... RESET bit, thus negating the software reset. Otherwise, the effect of a software reset is equivalent to that of a hardware reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RESET 0 TYPE[2] 0 TYPE[1] 0 TYPE[0] 1 ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 87 ...
Page 103
... If MINTE is logic 0, INTB is unconditionally high-impedance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Reserved 0 Reserved 0 LTXCINV 0 LRXCINV 0 RESETO 0 MINTE 0 RXAUTOSEL 1 ACTIVE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 88 ...
Page 104
... LTXD[15:0] bus is output on the rising edge of the clock signal input on the corresponding LTXC[15:0] line. Reserved: These bits must be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 89 ...
Page 105
... This bit is not self-clearing only cleared to logic 0 by reading the Receive Logical Channel FIFO Interrupt register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default UPCIFI X OCIF X ICIF X TFI X RFI X TXI X RX2I X RX1I X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 90 ...
Page 106
... Microprocessor Cell Buffer Interrupt register that has its corresponding enable set is a logic 1. This bit is not self-clearing only cleared to logic 0 by reading the Microprocessor Cell Buffer Interrupt register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 91 ...
Page 107
... Microprocessor RXD2 FIFO Interrupt Status register that has its corresponding enable set is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X UPFI X RCSDI X RBOCI X ROOLI X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 92 ...
Page 108
... This bit is not self-clearing only cleared to logic 0 by reading the RXD1 Extract FIFO Interrupt Status register or the Microprocessor RXD2 Extract FIFO Interrupt Status register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 93 ...
Page 109
... IFCLKA bit monitors the internally generated CSDCLK. This clock is generated by dividing the high-speed serial link clock by 6. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X ROOLE 0 ROOLV X REFCLKA X OFCLKA X IFCLKA X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 94 ...
Page 110
... When ROOLE and the Master Interrupt Enable bit of the Master Configuration register are set to logic one, the INTB output is asserted low when the ROOLV bit changes state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 95 ...
Page 111
... TXD1+/-. When LLB is logic one, the sliced receive data replaces the transmit data at the high-speed transmitter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RDIDIS2 0 RDIDIS1 0 TXDIS2 0 TXDIS1 0 MLB2 0 MLB1 0 DLB2 0 DLB1 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 96 ...
Page 112
... RDI codeword being transmitted in the BOC bit position . Note that RDI can be sent manually by writing all zeros to the TXD2 Transmit Bit Oriented Code register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 97 ...
Page 113
... XAD[11:0] bits are inserted in the 11 most significant bits of the Extended Address field of the prepend in 16 bit format. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default XAD[7] 0 XAD[6] 0 XAD[5] 0 XAD[4] 0 XAD[3] 0 XAD[2] 0 XAD[1] 0 XAD[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 98 ...
Page 114
... These are the three most significant bits of the Extended Address Match. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X XAD[10] 0 XAD[9] 0 XAD[8] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 99 ...
Page 115
... Extended Address Match bit value. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default XAM[7] 0 XAM[6] 0 XAM[5] 0 XAM[4] 0 XAM[3] 0 XAM[2] 0 XAM[1] 0 XAM[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 100 ...
Page 116
... These are the three most significant bits of the Extended Address Match. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X XAM[10] 0 XAM[9] 0 XAM[8] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 101 ...
Page 117
... OAD[4:0] bits of this register. OCAEN should only be set to logic 1 after the aforementioned register bits have been initialized. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X OCAEN 0 OAD[4] 0 OAD[3] 0 OAD[2] 0 OAD[1] 0 OAD[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 102 ...
Page 118
... When OMASTERV is low the, input port is configured as a bus slave. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X SCIANYV X OBUS8V X OANYPHYV X OMASTERV X IBUS8V X IANYPHYV X IMASTERV X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 103 ...
Page 119
... When SCIANYV is high, the SCI-PHY/Any-PHY interface is used to exchange cells with the DUPLEX. When SCIANYV is low, the Clocked Serial Data interface is used to exchange cells with the DUPLEX. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 104 ...
Page 120
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default H5UDF 1 Unused X Unused X Reserved 0 PRELEN[1] 0 PRELEN[0] 0 Unused X PTYP prepended word 01 “Word 1” only is included 10 “Word 1:” and “Word 2” are included PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Description 105 ...
Page 121
... H5 and UDF octets are included, i.e. the optional “Word 4” illustrated in Fig. 6 and Fig included in the 8-bit or 16-bit data structure expected on IDAT[15:0]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 106 ...
Page 122
... PHYDEV[1] 0 PHYDEV[0] 0 00000 Poll all 32 devices 00001 Poll PHY#1 thru PHY#2 00010 Poll PHY#1 thru PHY#3 00011 Poll PHY#1 thru PHY 11110 Poll PHY#1 thru PHY#31 11111 Poll all 32 PHY devices PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Description 107 ...
Page 123
... SCI-PHY/Any-PHY input port. If ENFLTR is set logic 0, all cells, including Physical Layer and unassigned cells are transferred over the SCI-PHY/Any- PHY input port. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 108 ...
Page 124
... When PARRERE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X PHYCELLE 0 CELLXFERRE 0 PARERRE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 109 ...
Page 125
... SCI-PHY/Any-PHY input port. This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X PHYCELLI 0 CELLXFERRI 0 PARERRI 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 110 ...
Page 126
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ICAEN[7] 1 ICAEN[6] 1 ICAEN[5] 1 ICAEN[4] 1 ICAEN[3] 1 ICAEN[2] 1 ICAEN[1] 1 ICAEN[0] 1 Function Default ICAEN[15] 1 ICAEN[14] 1 ICAEN[13] 1 ICAEN[12] 1 ICAEN[11] 1 ICAEN[10] 1 ICAEN[9] 1 ICAEN[8] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 111 ...
Page 127
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ICAEN[23] 1 ICAEN[22] 1 ICAEN[21] 1 ICAEN[20] 1 ICAEN[19] 1 ICAEN[18] 1 ICAEN[17] 1 ICAEN[16] 1 Function Default ICAEN[31] 1 ICAEN[30] 1 ICAEN[29] 1 ICAEN[28] 1 ICAEN[27] 1 ICAEN[26] 1 ICAEN[25] 1 ICAEN[24] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 112 ...
Page 128
... Setting the Input Cell Available registers to other values than the default value may cause the device to behave erratically when the S/UNI-DUPLEX is configured for Clocked Serial Data interface (SCIANY input is low). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 113 ...
Page 129
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CELLXFERRI X CELLXFERRE 0 Unused X INADDUDF 0 H5UDF 1 PRELEN[1] 0 PRELEN[0] 0 PTYP prepended word 01 “Word 1” only is included 10 “Word 1:” and “Word2” are included PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Description 114 ...
Page 130
... This interrupt status is asserted upon the selection by the external bus master of the SCI-PHY/Any- PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 115 ...
Page 131
... This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 116 ...
Page 132
... PHYDEV[1] 0 PHYDEV[0] 0 00000 Poll all 32 devices 00001 Poll PHY#1 thru PHY#2 00010 Poll PHY#1 thru PHY#3 00011 Poll PHY#1 thru PHY 11110 Poll PHY#1 thru PHY#31 11111 Poll all 32 PHY devices PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Description 117 ...
Page 133
... When BOCE and the Master Interrupt Enable bit of the Master Configuration register are set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 118 ...
Page 134
... BOCI will not be set at the transition to a validated IDLE code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default IDLEI X BOCI X BOC[5] X BOC[4] X BOC[3] X BOC[2] X BOC[1] X BOC[0] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 119 ...
Page 135
... Indication (RDI) is not currently being transmitted. The default value represents an idle code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 120 ...
Page 136
... EXCRCERRE is set to logic 1, the INTB output is asserted low when the EXTCRCERRI bit is logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default EXTCRCERRI X EXTRDYI X INSOVRI X INSRDYI X EXTCRCERRE 0 EXTRDYE 0 INSOVRE 0 INSRDYE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 121 ...
Page 137
... Extract CRC Accumulator register differs from the expected CRC-32 remainder polynomial. Otherwise set to logic 0. This bit is also reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 122 ...
Page 138
... Insert CRC-32 Accumulation register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X INSCRCEND 0 INSCRCPR 1 INSRST X Unused X Unused X Unused X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 123 ...
Page 139
... It is cleared on every read from normal mode Microprocessor Cell Data register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X EXTCRCCHK 0 EXTCRCPR 1 EXTABRT X Unused X Unused X EXTFSEL 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 124 ...
Page 140
... If EXTCRCCHK is logic 1, the EXTCRCERRI bit will be set to logic 1 if the CRC-32 value is incorrect. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 125 ...
Page 141
... Note that the INSRDY bit will always return a logic 0 if the FIFO is currently being written to. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X INSRDY X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 126 ...
Page 142
... Note that the EXTRDY bit for the FIFO currently being read will always return a logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X EXTRDY[1] X EXTRDY[0] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 127 ...
Page 143
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default INSCRCACC[7] 1 INSCRCACC[6] 1 INSCRCACC[5] 1 INSCRCACC[4] 1 INSCRCACC[3] 1 INSCRCACC[2] 1 INSCRCACC[1] 1 INSCRCACC[0] 1 Function Default INSCRCACC[15] 1 INSCRCACC[14] 1 INSCRCACC[13] 1 INSCRCACC[12] 1 INSCRCACC[11] 1 INSCRCACC[10] 1 INSCRCACC[9] 1 INSCRCACC[8] 1 Function Default INSCRCACC[23] 1 INSCRCACC[22] 1 INSCRCACC[21] 1 INSCRCACC[20] 1 INSCRCACC[19] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 128 ...
Page 144
... REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default INSCRCACC[18] 1 INSCRCACC[17] 1 INSCRCACC[16] 1 Function Default INSCRCACC[31] 1 INSCRCACC[30] 1 INSCRCACC[29] 1 INSCRCACC[28] 1 INSCRCACC[27] 1 INSCRCACC[26] 1 INSCRCACC[25] 1 INSCRCACC[24] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 129 ...
Page 145
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default EXTCRCACC[7] 1 EXTCRCACC[6] 1 EXTCRCACC[5] 1 EXTCRCACC[4] 1 EXTCRCACC[3] 1 EXTCRCACC[2] 1 EXTCRCACC[1] 1 EXTCRCACC[0] 1 Function Default EXTCRCACC[15] 1 EXTCRCACC[14] 1 EXTCRCACC[13] 1 EXTCRCACC[12] 1 EXTCRCACC[11] 1 EXTCRCACC[10] 1 EXTCRCACC[9] 1 EXTCRCACC[8] 1 Function Default EXTCRCACC[23] 1 EXTCRCACC[22] 1 EXTCRCACC[21] 1 EXTCRCACC[20] 1 EXTCRCACC[19] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 130 ...
Page 146
... REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default EXTCRCACC[18] 1 EXTCRCACC[17] 1 EXTCRCACC[16] 1 Function Default EXTCRCACC[31] 1 EXTCRCACC[30] 1 EXTCRCACC[29] 1 EXTCRCACC[28] 1 EXTCRCACC[27] 1 EXTCRCACC[26] 1 EXTCRCACC[25] 1 EXTCRCACC[24] 1 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 131 ...
Page 147
... REFCLK periods. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default MCDAT[7] X MCDAT[6] X MCDAT[5] X MCDAT[4] X MCDAT[3] X MCDAT[2] X MCDAT[1] X MCDAT[0] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 132 ...
Page 148
... RXD1+/-. When UPF1OVRE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X UPF1OVRE 0 UPF1RST 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 133 ...
Page 149
... The UPF1OVRI bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X UPF1OVRI 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 134 ...
Page 150
... RXD2+/-. When UPF2OVRE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X UPF2OVRE 0 UPF2RST 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 135 ...
Page 151
... The UPF2OVRI bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X UPF2OVRI 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 136 ...
Page 152
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FOVRE 0 FIFORST 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 137 ...
Page 153
... The FOVRE bit enables the assertion of the INTB output due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 138 ...
Page 154
... The FOVRI bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X FOVRI X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 139 ...
Page 155
... CRC-8 code word. The PREPEND PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default DDSCR 0 HDSCR 1 Unused X CNTCELLERR 0 CELLCRC 0 PREPEND 0 USRHDR[1] 1 USRHDR[0] 0 Bytes in User Header Reserved PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 140 ...
Page 156
... THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is descrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both descrambled. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER self-synchronous 141 ...
Page 157
... When OCDV is logic 0, the cell delineation PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X HCSPASS 0 Reserved 0 OCDV X Unused X ACTV X LCDV X LOSV X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 142 ...
Page 158
... Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 143 ...
Page 159
... ACTV register bit. When ACTE is set to logic 1, the INTB output is asserted low when the ACTI bit is logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X HCSE 0 XFERE 0 OCDE 0 CELLERRE 0 ACTE 0 LCDE 0 LOSE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 144 ...
Page 160
... HCS error counter holding registers. When XFERE is set to logic 1, the INTB output is asserted low when the XFERI bit is logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 145 ...
Page 161
... CRC-8 protecting the entire cell. This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default OVR X XFERI X HCSI X OCDI X CELLERRI X ACTI X LCDI X LOSI X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 146 ...
Page 162
... HCS error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 147 ...
Page 163
... Performance Meters (0x00) register, and remain valid until another transfer is triggered. The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default HCSERR[7] X HCSERR[6] X HCSERR[5] X HCSERR[4] X HCSERR[3] X HCSERR[2] X HCSERR[1] X HCSERR[0] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 148 ...
Page 164
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RCELL[7] X RCELL[6] X RCELL[5] X RCELL[4] X RCELL[3] X RCELL[2] X RCELL[1] X RCELL[0] X Function Default RCELL[15] X RCELL[14] X RCELL[13] X RCELL[12] X RCELL[11] X RCELL[10] X RCELL[9] X RCELL[8] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 149 ...
Page 165
... The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RCELL[23] X RCELL[22] X RCELL[21] X RCELL[20] X RCELL[19] X RCELL[18] X RCELL[17] X RCELL[16] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 150 ...
Page 166
... Master Configuration register are set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X FOVRE 0 FIFORST 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 151 ...
Page 167
... This bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X FOVRI X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 152 ...
Page 168
... Setting FDEPTH[5:0] to others values may cause FIFO malfunction. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X FDEPTH[5] 0 FDEPTH[4] 0 FDEPTH[3] 0 FDEPTH[2] 0 FDEPTH[1] 1 FDEPTH[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 153 ...
Page 169
... User Prepend byte is overwritten by the CRC-8 syndrome for the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default DSCR 0 HSCR 1 Unused X DHCS 0 CELLCRC 0 PREPEND 0 USRHDR[1] 1 USRHDR[0] 0 Bytes in User Header Reserved PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 154 ...
Page 170
... Cell payload and header scrambling is disabled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload is scrambled. Cell header is left unscrambled. THIS CONFIGURATION SHOULD ONLY BE USED FOR DIAGNOSTIC PURPOSES. Cell payload and header are both scrambled. PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 155 ...
Page 171
... Master Configuration register are set to logic 1, the INTB output is asserted low if the XFERI bit is a logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default XFERE 0 XFERI X OVR X Unused X Unused X Unused X Unused X Unused X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 156 ...
Page 172
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TCELL[7] X TCELL[6] X TCELL[5] X TCELL[4] X TCELL[3] X TCELL[2] X TCELL[1] X TCELL[0] X Function Default TCELL[15] X TCELL[14] X TCELL[13] X TCELL[12] X TCELL[11] X TCELL[10] X TCELL[9] X TCELL[8] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 157 ...
Page 173
... Load Performance Meters (0x00) register, and remain valid until another transfer is triggered. The count saturates at all ones. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TCELL[23] X TCELL[22] X TCELL[21] X TCELL[20] X TCELL[19] X TCELL[18] X TCELL[17] X TCELL[16] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 158 ...
Page 174
... CRWB triggers an indirect read operation. The data read can be found in the Receive Serial Indirect Channel Data registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CBUSY X CRWB 0 DRHCSE 0 Unused X CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 159 ...
Page 175
... Channel Data registers or to determine when a new indirect write operation may commence. The CBUSY is not expected to remain at logic 1 for more than two REFCLK cycles. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 160 ...
Page 176
... Reserved: This bit must be logic 0 for correct operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PROV 0 HCSPASS 0 UNASSFLTR 0 IDLEPASS 0 DDSCR 0 Reserved 0 DDELIN 0 Unused X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 161 ...
Page 177
... CHAN[3:0]. When PROV is set to logic 0, the TC processor will ignore data on the channel specified by CHAN[3:0]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 162 ...
Page 178
... When OOCDE is set to logic 1, the interrupt is enabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X OOCDE 0 HCSE 0 FOVRE 0 LCDE 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 163 ...
Page 179
... SYNC state or not. The OOCDI bit is reset immediately after a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default OOCDV X LCDV X Unused X Unused X OOCDI X HCSI X FOVRI X LCDI X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 164 ...
Page 180
... LCD Count Threshold register. OOCDV: The OOCDV bit is set to logic 1 when the logical channel is not currently in the SYNC state. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 165 ...
Page 181
... HCSERR[7:0] retains value of FFH until the next accumulation interval. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default HCSERR[7] X HCSERR[6] X HCSERR[5] X HCSERR[4] X HCSERR[3] X HCSERR[2] X HCSERR[1] X HCSERR[0] X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 166 ...
Page 182
... LCDC[7:0]. The default value of LCD[7:0] of 104 translates 600 kb/s. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCDC[7] 0 LCDC[6] 1 LCDC[5] 1 LCDC[4] 0 LCDC[3] 1 LCDC[2] 0 LCDC[1] 0 LCDC[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 167 ...
Page 183
... Channel Data registers or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default CBUSY X CRWB 0 Unused X Unused X CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 168 ...
Page 184
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default DHCS 0 HSCR 0 DSCR 0 Unused X Unused X Unused X Unused X Unused X PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 169 ...
Page 185
... DHCS reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 170 ...
Page 186
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X ALIGN 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 171 ...
Page 187
... Writable test mode register bits are not initialized upon reset unless otherwise noted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 172 ...
Page 188
... CSB pin low tri-states the data bus. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Reserved 0 PMCATST X PMCTST X DBCTRL X IOTST 0 HIZDATA X HIZIO 0 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 173 ...
Page 189
... RX8K output, as described in the following table: CLKSEL[2:0] 00000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X TCADIS 0 LINKSELBP 0 SELOCD 0 CKLSEL[2] 0 CLKSEL[1] 0 CLKSEL[0] 0 Clock RX8K PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 174 ...
Page 190
... The only other signals involved are the REFCLK, TCK and TX8K inputs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ACT_RCLK SYSCLK CSDCLK DCLK CCLK L1_RCLK L2_RCLK PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 175 ...
Page 191
... RAM The following procedure tests the two 2048x8 RAMs: simultaneously: 1. Hold REFCLK and TCK low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Expected D[7:0] xxxx0011 ...
Page 192
... Write the following register locations to select the test mode and initialize the BIST circuitry: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Expected D[7:0] xxxx0011 ...
Page 193
... Letting the test run indefinitely simply causes the test sequences to be repeated. A[7:0] 0xBE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Expected D[7:0] xxxx0011 178 ...
Page 194
... Boundary Scan 010 Bypass 011 Bypass 100 Boundary Scan 101 Bypass 110 Bypass 111 Cell Enable Pin/Enable Type ENABLE oavalid_lrxd_1 OUT_CELL oenb_lrxd_2 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER Register Cell Enable Bit Type 50 IO_CELL octrl_oen 51 IO_CELL octrl_oen 179 ...
Page 195
... PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 52 IO_CELL oca_oen 53 OUT_CELL 54 IO_CELL odat_oen 55 IO_CELL odat_oen 56 IO_CELL odat_oen 57 IO_CELL odat_oen ...
Page 196
... Fig. 12 Input Observation Cell (IN_CELL) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 IO_CELL octrl_oen idat_13_ltxc_12 ENABLE idat_14_ltxd_12 IO_CELL octrl_oen idat_15_ltxc_13 IO_CELL octrl_oen iprty_ltxd_13 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 96 IN_CELL 97 IO_CELL csd_oen 98 IN_CELL 99 IO_CELL ...
Page 197
... RELEASED DATA SHEET PMC-1980581 Fig. 13 Output Cell (OUT_CELL) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 182 ...
Page 198
... RELEASED DATA SHEET PMC-1980581 Fig. 14 Bidirectional Cell (IO_CELL) Fig. 15 Layout of Output Enable and Bidirectional Cells PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 183 ...
Page 199
... Insert CRC-32 Accumulator register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 184 ...
Page 200
... CRC-32 field check is done by setting the EXTCRCCHK bit of the Microprocessor Extract FIFO Control register to logic 1. This causes the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM7350 S/UNI DUPLEX DUAL SERIAL LINK PHY MULTIPLEXER 185 ...