CS5014-KP14 Cirrus Logic, Inc., CS5014-KP14 Datasheet
CS5014-KP14
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CS5014-KP14 Summary of contents
Page 1
... This allows throughput rates up to 100 kHz (CS5012A), 56 kHz (CS5014) and 50 kHz (CS5016). An evaluation board (CDB5012/14/16) is available which allows fast evaluation of ADC performance. ...
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CS5012A ANALOG CHARACTERISTICS VA-, VD- = -5V; VREF = 2.5V to 4.5V; f Parameter* Specified Temperature Range Accuracy Linearity Error Drift Differential Linearity Drift Full Scale Error Drift Unipolar Offset Drift Bipolar Offset Drift Bipolar Negative Full-Scale Error(Note 1) Drift ...
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CS5012A ANALOG CHARACTERISTICS Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode CS5012 CS5012A Bipolar Mode CS5012 CS5012A Conversion & Throughput Conversion Time -7 (Notes 5 and 6) -12 Acquisition Time -7 -12 Throughput -7 ...
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... Noise Unipolar Mode Bipolar Mode Notes detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28 for the CS5016. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. ...
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... CS5014 ANALOG CHARACTERISTICS Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion & Throughput Conversion Time -14 (Notes 5 and 6) -28 Acquisition Time -14 -28 Throughput -14 -28 Power Supplies DC Power Supply Currents Power Dissipation Power Supply Rejection ...
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CS5016 ANALOG CHARACTERISTICS VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -16, 2 MHz for -32; Analog Source Impedance = 200 ; Synchronous Sampling.) Parameter* Specified Temperature Range Accuracy Linearity Error ...
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CS5016 ANALOG CHARACTERISTICS Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion & Throughput Conversion Time -16 (Notes 5 and 6) -32 Acquisition Time -16 -32 Throughput -16 -32 Power Supplies DC ...
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... SWITCHING CHARACTERISTICS VA-, VD- = -5V 10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C Parameter CS5012A CLKIN Frequency: Internally Generated: Externally Supplied: CS5014/5016 CLKIN Frequency: Internally Generated: Externally Supplied: CLKIN Duty Cycle Rise Times: Fall Times: HOLD Pulse Width Conversion Time: Data Delay Time EOC Pulse Width ...
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... CAL, INTRLV HOLD EOC Output Data DS14F6 t fall t rise 90% 90% 10% 10% Rise and Fall Times t pwl t pwh Serial Output Timing Hi Read and Calibration Control Timing t hpw t c LAST CONVERSION DATA VALID Conversion Timing CS5012A, CS5014, CS5016 Hi epw t dd NEW DATA VALID 2-15 ...
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... VA+ Positive Analog Negative Analog VA- -4.5 VREF (Note 14) V AGND AIN V -VREF AIN (AGND, DGND = 0V, all voltages with repect to ground.) Symbol (Note 15) VD+ VD- VA+ VA- (Note 16 INA V IND stg CS5012A, CS5014, CS5016 Typ Max -40 A). OH out Typ Max 4.5 5.0 VA+ -5 ...
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... The conversion algorithm op- erates on this fixed charge, and the signal at the analog input pin is ignored. In effect, the entire DAC capacitor array serves as analog memory S1 To MCU CS5012A, CS5014, CS5016 C/X C/X Bit 0 Dummy LSB . Switch S1 is closed ...
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... CS5012A/14/16 Master Clock CLKIN (Optional) Figure 3a. Asynchronous Sampling 2-18 CS5012A, CS5014, CS5016 Auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. To achieve complete accuracy from the DAC, the CS5012A/14/16 use a novel self-calibration scheme. Each bit capacitor, shown in Figure 1, actually consists of several capacitors which can be manipulated to adjust the overall bit weight ...
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... This adds to the conversion time to define the converter’s maximum throughput. The con- version time of the CS5012A/14/16, in turn, depends on the sampling, calibration, and CLKIN conditions. Address Bus CS5012A/14/16 Figure 4b. Conversions under Microprocessor Control CS5012A, CS5014, CS5016 HOLD ADDR VALID AN Addr CS ...
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... Master Clock Period) clk CS5012A, CS5014, CS5016 1 / Throughput ( cycles) Conversion ( cycles) * Acquisition (15 cycles) CS5014 CS5016 CLK for CS5016 where f CLK Throughput Time Min ...
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... CLKIN cycles plus 2.25 CS5012A -7 version only) must be allowed for signal acquisition before HOLD is activated. Un- der microprocessor-independent operation (CS, RD low; A0 high) the CS5014’s and CS5016’s EOC output will not fall at the completion of the calibration cycle, but EOT will fall 15 CLKIN cycles later. ...
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... CS5012A and one calibration per 72,051 conversions in the CS5012, CS5014 and CS5016). Initiated by bringing both the INTRLV input and CS low (or hard-wiring INTRLV low), interleave extends the CS5012A/14/16’s effective conversion time by 20 CLKIN cycles ...
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... To interface with a 16-bit data bus, the BW input to the CS5012A/14/16 should be held high and all data bits (12, 14 and 16 for the CS5012A, CS5014 and CS5016 respectively) read in paral- lel on pins D4-D15 (CS5012A), D2-D15 (CS5014), or D0-D15 (CS5016). With an 8-bit bus, the converter’s result must be read in two portions. In this instance, BW should be held low and the 8 MSB’ ...
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... As the analog input signal varies, the switching sequence of the inter- nal capacitor array changes. The current load on the external reference circuitry thus varies in re- sponse with the analog input. Therefore, the external reference must not exhibit significant CS5012A, CS5014, CS5016 DS14F6 ...
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... CLKIN cycles after a data read (Microprocessor Mode CLKIN cycles after HOLD = 0 is recognized on a rising edge of CLKIN/4. DS14F6 pedance of less than 15 than 10 kHz. Similarly, for the CS5014 with a 4.5V reference (275 V/LSB), better than 1/4 LSB accuracy can be insured with an output impedance ...
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... The recommended refer- ence voltage is between 2.5 and 4.5 V for the CS5012A and 4.5 V for the CS5014/16. The CS5012A/14/16 can actually accept reference voltages up to the positive analog supply. How- ever, the buffer’s offset may increase as the reference voltage approaches VA+ thereby in- creasing external drive requirements at VREF ...
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... CS5014/16 can slew at 5V bipolar mode, only half the capacitor array is connected to the analog input so the CS5012A can slew at 40V/ s, and the CS5014/16 can slew at 10V/ s. After the first six CLKIN cycles, the CS5012A will slew at 1.25V unipolar mode and 3.0V bipolar mode, and the CS5014/16 will slew at 0 ...
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... AGND pin, which should be used as the entire system’s analog ground reference point. 2-28 CS5012A, CS5014, CS5016 The digital and analog supplies to the CS5012A/14/16 are pinned out separately to minimize coupling between the analog and digital sections of the chip ...
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... Bows in the transfer curve generate harmonic distortion. The worst-case condition of bit-weight errors (DNL) has traditionally also de- fined the point of maximum INL. 1 MHz Bit-weight errors have a drastic effect on a con- verter’s ac performance. They can be analyzed as step functions superimposed on the input signal. CS5012A, CS5014, CS5016 2-29 ...
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... Codes Figure 14. CS5012A Differential Nonlinearity Plot 2,048 Codes Figure 15. CS5012 Differential Nonlinearity Plot 8,192 Codes Figure 16. CS5014 Differential Nonlinearity Plot 32,768 Codes Figure 17. CS5016 Differential Nonlinearity Plot CS5012A, CS5014, CS5016 4,095 4,095 16,383 65,535 DS14F6 ...
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... CS5012A calibrates its bit weight errors to a small fraction of an LSB at 12-bits yielding peak distortion below the noise floor (see Figure 19). The CS5014 calibrates its bit weights to within 1/16 LSB at 14-bits ( 0.0004% FS) yielding peak distortion as low as -105 dB (see Fig- ure 22). The CS5016 calibrates its bit weights to within 1/4 LSB at 16-bits ( 0 ...
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... FFT’s and windowing refer to: F.J. HARRIS, "On the use of windows for harmonic S/(N+D): 86.1 dB Signal Amplitude Relative to Full Scale Figure 22. CS5014 FFT plot with 1 kHz CS5012A, CS5014, CS5016 0.0 Sampling Rate: 100kHz Full Scale: 9Vp-p S/N+D: 73.6dB dc 1.0 Input Frequency (kHz) ...
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... Nyquist rate. Best performance at the higher frequencies is achieved with a 2.5 volt reference 100 Input Frequency (kHz) CS5012A, CS5014, CS5016 0dB Sampling Rate: 50 kHz -20dB Full Scale: 9V p-p S/(N+D): 92.4 dB -40dB -60dB -80dB -100dB -120dB 1 kHz dc Input Frequency Figure 24 ...
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... Analog Input Amplitude Figure 28. CS5016 S/(N+D) vs. Input Amplitude (9Vp-p Full-Scale Input) Signal to Noise + Distortion vs Signal Level As illustrated in Figures 26 - 29, the CS5014/16’s on-chip self-calibration provides very accurate bit weights which yield no degradation in quantiza- tion noise with low-level input signals. In fact, quantization noise remains below the noise floor in the CS5016, which dictates the converter’ ...
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... Since the CS5014/16 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converter’s HOLD input falls. It need only acquire the analog input by the time the entire conversion cycle finishes ...
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... External External External External Figure 35. Examples of Measured Clock Feedthrough If sampling is performed asynchronously with the master clock, clock feedthrough will appear error at the CS5014/16’s output. With a fixed CS5012A, CS5014, CS5016 0dB Sampling Rate: 56 kHz -20dB Full Scale: 9V p-p S/(N+D): 64.6 dB -40dB ...
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... Also, the overall effect of clock feedthrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5014/16 can be op- erated in bipolar mode which inherently doubles the LSB size over the unipolar mode. DS14F6 ...
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... CLKIN cycles for CLKIN=4MHz, but will require 68 CLKIN cycles at 100kHz through- put. This is due to excess delay on 275pF typical, unipolar mode 165pF typical, bipolar mode 20V/us 1.5V/us 40V/us 3.0V/us CS5012A, CS5014, CS5016 CS5012 EOT falls 15 CLKIN EOT. 5V/us 0.25V/us 10V/us 0.5V/us DS14F6 ...
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... RESET 31 27 AGND TST 10 29 REFBUF DGND 0.1 F VA- VD- 0 CS5012A, CS5014, CS5016 RST Function Hold and Start Convert 0 Initiate Burst Calibration 0 Stop Burst Cal and Begin Track 0 Initiate Interleave Calibration 0 Terminate Interleave Cal 0 0 Read Output Data 0 Read Status Register ...
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... HOLD CS5016 (LSB) DATA BUS BIT 0 DATA BUS BIT 1 CS5014 (LSB) DATA BUS BIT 2 DATA BUS BIT 3 CS5012 (LSB) DATA BUS BIT 4 DATA BUS BIT 5 DATA BUS BIT 6 DATA BUS BIT 7 DIGITAL GROUND POSITIVE DIGITAL POWER DATA BUS BIT 8 DATA BUS BIT 9 ...
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... RD – Read, PIN 22. When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW and A0. DS14F6 CS5012A, CS5014, CS5016 2-41 ...
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... CAL is latched low again. Calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/ the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning ...
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... REFBUF – Reference Buffer Output, PIN 29. Reference buffer output. A 0.1 F ceramic capacitor must be tied between this pin and VA-. Miscellaneous TST – Test, PIN 31. Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be tied to DGND. DS14F6 CS5012A, CS5014, CS5016 2-43 ...
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... The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. 2-44 CS5012A, CS5014, CS5016 DS14F6 ...
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... CS5012-TD12B 5962-897901QA CS5012-TE24B 5962-897901XA CS5012-TE12B 5962-897901XA 40 pin DIP 40 pin DIP 40 pin DIP 44 pin PLCC 44 pin PLCC 44 pin PLCC CS5012A, CS5014, CS5016 Temp. Range Package 40-Pin Plastic DIP 40-Pin Plastic DIP 44-Pin PLCC 44-Pin PLCC -40 to +85 C 40-Pin Plastic DIP -40 to +85 C ...
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... CS5014 Ordering Guide Model Throughput CS5014-KP28 28 kHz CS5014-KP14 56 kHz CS5014-KL28 28 kHz CS5014-KL14 56 kHz CS5014-BP28 28 kHz CS5014-BP14 56 kHz CS5014-BL28 28 kHz CS5014-BL14 56 kHz CS5014-SD14 56 kHz CS5014-TD14 56 kHz CS5014-SE14 56 kHz CS5014-TE14 56 kHz 5962-8967401QA 56 kHz 5962-8967402QA 56 kHz 5962-8967401XA 56 kHz 5962-8967402XA 56 kHz The following is a list of upgraded part numbers. ...
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... Discontinued Part Number Recommended Device CS5016-SD16B 5962-8967601QA CS5016-TD16B 5962-8967602QA CS5016-SE16B 5962-8967601XA CS5016-TE16B 5962-8967602XA CS5012A, CS5014, CS5016 Package 40-Pin Plastic DIP 40-Pin Plastic DIP 40-Pin Plastic DIP 40-Pin Plastic DIP 44-Pin PLCC 44-Pin PLCC 44-Pin PLCC 44-Pin PLCC -40 to +85 C ...
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D SEATING PLANE B1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. ...
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D2/E2 44 pin PLCC MILLIMETERS E DIM MIN A 4.20 A1 2.29 B 0.33 D/E 17.40 D1/E1 16.51 D2/E2 14.99 e 1.19 A NO. OF TERMINALS INCHES NOM MAX MIN NOM MAX 4.45 4.57 ...
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D SEATING PLANE B1 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.13mm (0.005") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 21 ...
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Top View 28/44 pin CLCC NO. OF TERMINALS 28 MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX A 2.54 3.05 3.43 0.100 0.120 0.135 0.33 0.46 0.58 0.013 0.018 0.023 B ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...