W83194BR-640 Winbond, W83194BR-640 Datasheet
W83194BR-640
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W83194BR-640 Summary of contents
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... Winbond for any damages resulting from such improper use or sales. 166MHZ CLOCK FOR SIS CHIPSET W83194BR-640 Data Sheet Revision History Version On Web n.a. All of the versions before 0.50 are for internal use. 1.0 Change version and version on web site to 1 W83194BR-640 Main Contents Publication Release Date: April. 2001 Revision 1.0 ...
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... RESET# pin will output 4ms pulse signal. Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I The W83194BR-640 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50± ...
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... Vss I Crystal input with internal loading capacitors and feedback resistors. 7 OUT Crystal output at 14.318MHz nominally W83194BR-640 VddAPIC IOAPIC0 Vss VddC CPUCLK0T CPUCLK0C Vss VddC CPUCLK1T Vss Reserved RESET# VddSD SDRAM_out VssD PCI_STOP# CPU_STOP# PD# SDRAM_STOP# AGP_STOP# SDATA* SDCLK* Vss Vdd FUNCTION Publication Release Date: April. 2001 ...
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... I/O 2 I/O 3.3V, 14.318MHz reference clock output. Internal 120kΩ pull-down.This pin has 1.5X drive strength. Latched input for selecting the output frequency of CPU, SDRAM and - 4 - W83194BR-640 FUNCTION FUNCTION 2 C 2-wire control interface 2 C 2-wire control interface FUNCTION FS0 at initial power up for H/W Publication Release Date: April ...
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... CPUCLK1T, IOAPIC0, 2.5V. 17 Power supply for AGP outputs. 11 Power supply for PCI outputs. 36 Power supply for SDRAM and 48/24MHz outputs. 21 Power supply for 48/24MHz outputs W83194BR-640 This pin has 1.5X drive FUNCTION FUNCTION Publication Release Date: April. 2001 Revision 1.0 pull- ...
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... All proceeding bytes must be sent to change one of the control bytes. The 2-wire control interface allows each clock output individually enabled or disabled. W83194BR-640 initializes with default register settings, and then it ptional to use the 2-wire control interface. The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high during normal data transfer ...
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... SSEL1 (for frequency table selection by software via I SSEL0 (for frequency table selection by software via Selection by hardware 1 = Selection by software I SSEL4 (for frequency table selection by software via I SSEL5 (for frequency table selection by software via Running 1 = Tri-state all outputs - 7 - W83194BR-640 Byte0,1,2... Ack until Stop Byte2, 3, 4... Ack until Stop Description 2 ...
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... W83194BR-640 6 8 66.6 66.6 33.3 66 100 100 33.3 66 166 166 33.2 62 133 133 33.3 66 66.6 100 33.3 66 100 66.6 33.3 66 100 133 33.3 66 133 100 33.3 66 112 112 37.3 67 124 124 ...
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... W83194BR-640 6 8 108 108 130 130 32 135 135 33.75 67.5 50. 136 136 139 139 34.75 69.5 52. 140 140 142 142 35 143 143 35.75 71.5 53. 145 145 36.25 72.5 54. 130 130 26 6 ...
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... PCICLK1 (Active / Inactive) PCICLK_F (Active / Inactive) 24_48MHz (Active / Inactive) 48MHz (Active / Inactive) IOAPIC0 (Active/Inactive) - 24/48 MHz Frequency Control 1=24MHz 0=48MHz - IOAPIC Frequency Control 1=PCI / 2, 0=PCI - Reserved 3 REF1 (Active / Inactive) 2 REF0 (Active / Inactive W83194BR-640 Description Description Description Publication Release Date: April. 2001 Revision 1.0 ...
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... CPU_STOP# Latched PCI_STOP# Latched SDR_STOP# Latched PD# Description Enable Count 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count W83194BR-640 1=CPUCLK1 can stopped Publication Release Date: April. 2001 Revision 1.0 by ...
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... N value bit 1 N value bit 0 Register Description Spread spectrum up count 3 Spread spectrum up count 2 Spread spectrum up count 1 Spread spectrum up count 0 Spread spectrum down count 3 Spread spectrum down count 2 Spread spectrum down count 1 Spread spectrum down count W83194BR-640 Publication Release Date: April. 2001 Revision 1.0 ...
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... Reserve Reserve Reserve Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Version ID Version ID Version ID Version W83194BR-640 Publication Release Date: April. 2001 Revision 1.0 ...
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... SSEL3 SSEL2 SSEL1 SSEL0 ratio VCO/ CPU SDRAM PCI ratio ratio W83194BR-640 Ratio Selection Table 1 Reg10 Reg10 Reg10 bit2 bit1 bit0 VCO/AGP AGP2 AGP1 AGP0 ratio Publication Release Date: April. 2001 Publication Release Date: April. 2001 Revision 1.0 Revision 1.0 ...
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... W83194BR-640 8. HOW TO READ THE TOP MARKING W83194BR-630 28051234 942GED 1st line: Winbond logo and the type number: W83194BR-640 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 942 942: packages made in '99, week 42 G: assembly house ID ...
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... Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 16 - W83194BR-640 Winbond Electronics (North America) Corp. 2727 North First Street San Jose, California 95134 TEL: 1-408-9436666 FAX: 1-408-9436668 Publication Release Date: April. 2001 ...