CY7C1386B-133BZC Cypress Semiconductor Corporation., CY7C1386B-133BZC Datasheet
CY7C1386B-133BZC
Related parts for CY7C1386B-133BZC
CY7C1386B-133BZC Summary of contents
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... Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The CY7C1386B and CY7C1387B are both double-cycle SRAMs integrate deselect parts. All inputs and outputs of the CY7C1386B and the CY7C1387B are JEDEC-standard JESD8-5-compatible. 200 MHz 167 MHz 3 3 ...
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... Logic Block Diagram CY7C1386B — 512K × 36 CLK ADV ADSC ADSP A [18: BWE CY7C1387B — 1M × 18 Logic Block Diagram CLK ADV ADSC ADSP A [19: BWE Document #: 38-05195 Rev. ** ...
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... DQa DPb 57 24 DQa SSQ SSQ DDQ DDQ DQa DQa DQPa 30 CY7C1386B CY7C1387B DDQ V 76 SSQ NC 75 DPa 74 DQa 73 DQa SSQ V 70 DDQ DQa 69 DQa 68 CY7C1387B (1M × ...
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... DDQ DQb J V DDQ DQb M V DDQ N DQb 64M U V DDQ Document #: 38-05195 Rev. ** 119-Ball BGA — Top View CY7C1386B (512K × 36 ADSP ADSC DQPc DQc V CE1 V SS ...
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... DQb DQb DQb DPb 64M R MODE 32M Document #: 38-05195 Rev. ** 165-Ball Bump FBGA CY7C1386B (512K × 36) — 11 × 15 FBGA BWc BWb BWd BWa CLK DDQ DDQ DD SS ...
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... A rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and d are 1 bit wide. CY7C1386B CY7C1387B ...
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... Power supply for the I/O circuitry. Should be connected to a 2.5V – 3.3V –5% +10% power supply (see page 20). Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Pins are not internally connected. No connects. Reserved for address expansion. Pins are not internally connected. CY7C1386B CY7C1387B Page ...
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... Bytes not selected during a byte Write operation will remain unaltered. A synchronous 1 self-timed Write mechanism has been provided to simplify Write operations. Because the CY7C1386B/CY7C1387B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQ drivers safety precaution, DQ three-stated whenever a write cycle is detected, regardless of the state of OE ...
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... ZZ Mode Electrical Characteristics Parameter Description Fourth Address I DDZZ A [1:0] [1: ZZS ZZREC 01 10 CY7C1386B CY7C1387B after the ZZ input returns ZZREC Test Conditions Min. Max. Unit Sleep mode ZZ > V – 0.2V DD standby current Device ZZ > V – 0.2V DD operation recovery ZZ < 0.2V 2t ...
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... CY7C1386B CY7C1387B ADSC ADV ...
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... BWE Writes may occur only on subsequent clocks after x CY7C1386B CY7C1387B BWc BWb BWa ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1386B/CY7C1387B incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1386B CY7C1387B Page ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05195 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1386B CY7C1387B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... Boundary Scan Register TAP Controller [9, 10] Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ /2, Undershoot:V (AC)<0.5V for t<t /2, Power-up TCYC CY7C1386B CY7C1387B 0 Selection Circuitry Min. Max. 2 0.2 DD 0.4 0.2 1 0.5 0 <2.6V and V <2.4V and V <1.4V for t<200 ms. IH ...
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... CS CH 12. Test conditions are specified using the load in TAP AC test conditions. TR/ ns. Document #: 38-05195 Rev. ** [11 ,12] Over the Operating Range Description CY7C1386B CY7C1387B Min. Max. Unit 100 ns 10 MHz ...
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... TDOX TDOV CY7C1386B CY7C1387B 1.50V t TCYC ...
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... Do Not Use. This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1386B CY7C1387B Description Reserved for version number. Defines depth of SRAM. 512K or 1M. ...
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... CLK DQd MODE 3R 29 BWa BWb CE DQb CY7C1386B CY7C1387B Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb ...
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... IN DDQ 6.7-ns cycle, 150 MHz 1/t MAX CYC 7.5-ns cycle, 133 MHz Max Device All Speeds DD Deselected CY7C1386B CY7C1387B Ambient [14.] Temp DDQ 0°C to +70°C 3.3V 2.5V –5% –5%/+10% 3.3V + 10% -40°C to +85°C Min. Max. 3.135 3.63 2.375 3.63 2.375 ...
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... Document #: 38-05195 Rev. ** Test Conditions T 25° MHz 3.3 DDQ [16 317 V DDQ OUTPUT 351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1386B CY7C1387B Max [16] ALL INPUT PULSES 3.0V 90% 90% 10% GND 1 V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6.33 44 ...
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... AC test loads. Transition is measured 200 mV from steady-state CHZ CLZ OEV EOLZ EOHZ voltage. 19. At any given voltage and temperature, t Document #: 38-05195 Rev. ** [17,18,19] –200 Min. Max. 5.0 1.8 1.8 1.4 0.4 3.0 1.5 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 1.4 0.4 3.0 1.3 [18,19] 4.0 [18,19] 0 [18] 3.0 is less than t and t is less than t EOHZ EOLZ CHZ CLZ CY7C1386B CY7C1387B –167 –150 –133 Min. Max. Min. Max. Min. 6.0 6.7 7.5 2.1 2.3 2.5 2.1 2.3 2.5 1.5 1.5 1.5 0.5 0.5 0.5 3.4 3.8 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 1.5 1.5 1.5 0.5 0.5 0.5 1.5 1.5 1.5 ...
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... CY7C1386B CY7C1387B Pipelined Write Unselected ...
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... CY7C1386B CY7C1387B Unselected Pipelined Read inactive ...
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... CY7C1386B CY7C1387B Unselected Pipelined Read inactive ...
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... CY7C1386B CY7C1387B ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 26. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05195 Rev EOV t EOHZ Three-State t EOLZ t ZZS I (active DDZZ Three-state CY7C1386B CY7C1387B t ZZREC Page ...
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... CY7C1386B-167BGC 150 CY7C1386B-150BGC 133 CY7C1386B-133BGC 200 CY7C1387B-200BGC 167 –167BGC 150 –150BGC 133 –133BGC 200 CY7C1386B-200BZC 167 CY7C1386B-167BZC 150 CY7C1386B-150BZC 133 CY7C1386B-133BZC 200 CY7C1387B-200BZC 167 –167BZC 150 –150BZC 133 –133BZC 167 CY7C1386B-167AI 150 CY7C1386B-150AI 133 CY7C1386B-133AI 167 –167AI 150 –150AI 133 –133AI ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) Document #: 38-05195 Rev. ** CY7C1386B CY7C1387B 51-85050-A Page ...
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... Package Diagrams (continued) Document #: 38-05195 Rev. ** 119-Ball BGA (14 × 22 × 2.4 mm) CY7C1386B CY7C1387B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA (13 × 15 × 1.2 mm) BB165A CY7C1386B CY7C1387B Page ...
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... Revision History Document Title: CY7C1386B/CY7C1387B 512K x 36/ Pipelined DCD SRAM Document Number:38-05195 ISSUE REV. ECN NO. DATE ** 112030 12/09/01 Document #: 38-05195 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01117 to 38-05195 CY7C1386B CY7C1387B Page ...