CY2277APVC-3 Cypress Semiconductor Corporation., CY2277APVC-3 Datasheet

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CY2277APVC-3

Manufacturer Part Number
CY2277APVC-3
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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7A
Features
Functional Description
The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel
82430TX or similar chipsets. There are three available options
as shown in the selector guide
The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.
Cypress Semiconductor Corporation
Document #: 38-07332 Rev. *A
PWR_DWN
Logic Block Diagram
• Mixed 2.5V and 3.3V operation
• Complete clock solution to meet requirements of Pen-
• Factory-EPROM programmable CPU, PCI, and USB/IO
• Factory-EPROM programmable output drive and slew
• MODE Enable pin for CPU_STOP and PCI_STOP
• SMBus serial configuration interface
• Available in space-saving 48-pin SSOP and TSSOP
XTALOUT
Mobile PCs with Intel
tium
clock frequencies for custom configuration
rate for EMI customization
packages.
XTALIN
SDATA
— Four CPU clocks at 2.5V or 3.3V
— Up to eight 3.3V SDRAM clocks
— Seven 3.3V synchronous PCI clocks, one free
— Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable
— One 2.5V IOAPIC clock at 14.318 MHz
— Two 3.3V Ref. clocks at 14.318 MHz
MODE
SCLK
running
by serial interface
SEL
®
Pentium
, Pentium
14.318
OSC.
MHz
INTERFACE
®
CONTROL
SERIAL
LOGIC
II, 6x86, or K6 motherboards
®
/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/
EPROM
CPU
SYS
PLL
PLL
Delay
/2
Divide and
Mux Logic
STOP
LOGIC
®
3901 North First Street
82430TX and 2 DIMMs or 3 SO-DIMMs
STOP
LOGIC
®
PCICLK_F
USBCLK/IOCLK[0:1]
SDRAM[0–5]
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
PCI[0–5]
V
REF [0–1]
(14.318)
The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip,
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2277A Selector Guide
Note:
IOAPIC (14.318 MHz)
DDCPU
CPUCLK[0–3]
1.
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus select-
able)
PCI (CPU/2)
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
CPU-PCI delay
V
DDQ2
One free-running PCI clock.
Clock Outputs
enabling
San Jose
USBCLK/IOCLK
USBCLK/IOCLK
glitch-free
PCICLK_F
XTALOUT
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
XTALIN
SDATA
MODE
V
V
V
REF1
REF0
SCLK
1–6 ns 1–6 ns
-1/-1M
Pin Configuration
DDQ3
DDQ3
DDQ3
SEL
V
V
V
V
7
6/8
SS
SS
SS
SS
--
--
CA 95134
4
2
1
2
[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
Revised December 7, 2002
SSOP
transitions.
7
6/8
-3
--
4
--
2
1
2
[1]
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CY2277A
<1 ns
-7M
7
6/8
AV
PWR_SEL
V
IOAPIC
PWR_DWN
V
CPUCLK0
CPUCLK1
V
CPUCLK2
CPUCLK3
V
SDRAM0
SDRAM1
V
SDRAM2
SDRAM3
V
SDRAM4
SDRAM5
V
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AV
--
--
408-943-2600
4
2
1
2
[1]
DDQ2
SS
DDCPU
SS
DDQ3
SS
DDQ3
DD
DD
When
1–4 ns
-12M/
-12/
-12I
7
6/8
--
--
4
2
1
2
[1]
the

Related parts for CY2277APVC-3

CY2277APVC-3 Summary of contents

Page 1

Pentium /II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel Features • Mixed 2.5V and 3.3V operation • Complete clock solution to meet requirements of Pen- tium ® , Pentium ® II, 6x86 motherboards ...

Page 2

Pin Summary Name Pins V 7, 15, 21, 28, 34 DDQ3 V 46 DDQ2 V 40 DDCPU AV 25 10, 17, 24, 31, 37, 43 Ground SS [2] XTALIN 4 [2] XTALOUT 5 MODE 6 SEL ...

Page 3

Function Table (-1, -1M, -7M, -12, -12M, -12I) CPUCLK[0:3] SEL XTALIN SDRAM[0:7] 0 14.318 MHz 60.0 MHz 1 14.318 MHz 66.67 MHz Function Table (-3) CPUCLK[0:3] SEL XTALIN SDRAM[0:7] 0 14.318 MHz 33.33 MHz 1 14.318 MHz 66.67 MHz Actual ...

Page 4

Power Management Logic CPU_STOP PCI_STOP PWR_DWN Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte ...

Page 5

Byte 1: CPU, 24/48 MHz Active/Inactive Register (1 = Active Inactive), Default = Active Bit Pin # Description Bit 7 23 48/24 MHz (Active/Inactive) Bit 6 22 48/24 MHz (Active/Inactive) Bit 5 -- (Reserved) drive to ‘0’ Bit ...

Page 6

Operating Conditions Parameter Analog and Digital Supply Voltage DD DDQ3 V 2.5V CPU Supply Voltage (-1,-1M, -3, -7M) DDCPU 2.5V CPU Supply Voltage (-12, -12M, -12I) 3.3V CPU Supply Voltage V 2.5V IOAPIC Supply Voltage (-1,-1M, ...

Page 7

Electrical Characteristics (-1, -3, -12) Parameter Description Notes: 6. Electrical parameters are guaranteed with these operating conditions. 7. Guaranteed by design and characterization. Not 100% tested in production. 8. Power supply current will vary with number of outputs which are ...

Page 8

Electrical Characteristics (-12I) Parameter Description V High-level Input Voltage IH V Low-level Input Voltage IL V Low-level Input Voltage ILiic V High-level Output Voltage OH V Low-level Output Voltage OL V High-level Output Voltage OH V Low-level Output Voltage OL ...

Page 9

Switching Characteristics (-1, -3) Parameter Output Description t CPUCLK Output Duty Cycle 1 SDRAM USBCLK IOCLK REF [0,1] IOAPIC t PCI Output Duty Cycle 1 t CPUCLK, CPU and IOAPIC Clock 2 IOAPIC Rising and Falling Edge Rate t PCI ...

Page 10

Switching Characteristics (-1M, -7M, -12M) Parameter Output Description t CPUCLK Output Duty Cycle 1 SDRAM USBCLK REF [0,1] IOAPIC t PCI Output Duty Cycle 1 t CPUCLK, CPU and IOAPIC Clock 2 IOAPIC Rising and Falling Edge Rate t PCI ...

Page 11

Switching Characteristics (-12) Parameter Output Description t All Clocks Output Duty Cycle 1 t CPUCLK, CPU and IOAPIC Clock 2 IOAPIC Rising and Falling Edge Rate t PCI PCI Clock Rising and 2 Falling Edge Rate t REF0 REF0 Clock ...

Page 12

Switching Characteristics (-12I) Parameter Output Description t All Clocks Output Duty Cycle 1 t CPUCLK, CPU and IOAPIC Clock 2 IOAPIC Rising and Falling Edge Rate t PCI PCI Clock Rising and 2 Falling Edge Rate t REF0 REF0 Clock ...

Page 13

Timing Requirement for the SMBus Parameter t SCLK Clock Frequency 10 t Time the bus must be free before a new transmission can start 11 t Hold time start condition. After this period the first clock pulse is generated. 12 ...

Page 14

Switching Waveforms (continued) CPU-CPU Clock Skew CLK CLK t 5 CPU-SDRAM Clock Skew CPUCLK SDRAM t 7 CPU-PCI Clock Skew CPUCLK PCICLK t 6 [13, 14] CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) Notes: 13. CPUCLK on ...

Page 15

Switching Waveforms (continued) [15, 16] PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and ...

Page 16

Application Information Clock traces must be terminated with either series or parallel termination normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C this ...

Page 17

... Test Circuit Note: All capacitors should be placed as close to each pin as possible. Ordering Information Ordering Code CY2277APVC-1 CY2277APAC-1M CY2277APVC-3 CY2277APAC-7M CY2277APVC-12 CY2277APAC-12M CY2277APVI-12 Intel and Pentium are registered trademarks of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. ...

Page 18

Package Diagrams 48-Lead Thin Shrunk Small Outline Package, Type mm) Z48 Document #: 38-07332 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes ...

Page 19

Document Title: CY2277A Pentium and 2 DIMMs or 3 SO-DIMMs Document Number: 38-07332 Issue REV. ECN NO. Date ** 111731 12/15/01 *A 121855 12/14/02 Document #: 38-07332 Rev. *A ® /II, 6x86, K6 Clock Synthesizer/Driver for Desktop/Mobile PCs with Intel ...

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