cy2277a Cypress Semiconductor Corporation., cy2277a Datasheet
cy2277a
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cy2277a Summary of contents
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... II, 6X86, and K6 portable PCs designed with the Intel 82430TX or similar chipsets. There are three available options as shown in the selector guide The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up to nine selectable frequencies. There are up to eight 3.3V SDRAM clocks and seven PCI clocks, running at one half the CPU clock frequency ...
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... SDRAM clock outputs, have same frequency as CPU clocks CPU clock outputs PCI clock outputs PCI clock output, free-running IOAPIC clock output Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load USB or IO clock outputs, frequency selected by serial word = 18 pF. LOAD CY2277A is at 2.5V or 3.3V DDCPU ) DD Page ...
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... Actual • Output impedance: 25 (typical) measured at 1.5V (MHz) PPM –195 0 167 167 REF[0:1] IOAPIC USBCLK / IOCLK 14.318 MHz 48.0 MHz / 24.0 MHz 14.318 MHz 48.0 MHz / 24.0 MHz REF[0:1] IOAPIC USBCLK / IOCLK 14.318 MHz 48.0 MHz / 24.0 MHz 14.318 MHz 48.0 MHz / 24.0 MHz CY2277A [3] [3] Page ...
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... The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits Byte 1 - Bits Byte N - Bits • Reserved and unused bits should be programmed to “0”. • SMBus Address for the CY2277A is ...
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... Bit 1 N/A Not used, drive to ‘0’ Bit 0 N/A Not used, drive to ‘0’ Byte 6: Reserved, for future use Junction Temperature............................................... +150 C Package Power Dissipation.............................................. 1W + 0.5 DD Static Discharge Voltage............................................ >2000V (per MIL-STD-883, Method 3015, like V CY2277A Description Description pins tied together) DD Page ...
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... PWR_SEL 0V, PWR_SEL only IL Three-state V = 3.465V Loaded Outputs, CPU = 66.67 MHz 3.465V Unloaded Outputs Current draw in power-down state, PWR_SEL = V CY2277A Min. Max. Unit 3.135 3.465 V 2.375 2.9 V 2.375 2.625 3.135 3.465 2.375 2.9 V 2.375 2.625 3.135 3.465 ...
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... PWR_SEL 0V, PWR_SEL only IL Three-state V = 3.465V Loaded Outputs, CPU = 66.67 MHz 3.465V Unloaded Outputs Current draw in power-down state, PWR_SEL = V CY2277A Min. Max. Unit Min. Max. Unit 2.0 0.8 0 12.6 mA CPUCLK 1. 16.7mA IOAPIC 18.2 mA CPUCLK 0 23.1 mA IOAPIC ...
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... PWR_SEL 0V, PWR_SEL only IL Three-state V = 3.465V Loaded Outputs, CPU = 66.67 MHz 3.465V Unloaded Outputs Current draw in power-down state, PWR_SEL = V CY2277A Min. Max. Unit 2.0 0.8 0 CPUCLK 1. IOAPIC CPUCLK 0 ...
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... Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V for 3.3V clocks Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabiliza- tion from power-up Rate of change of frequency = 2.5V 3.3V. DDQ2 DDQ3 = 3.3V. When V = 2.5V, CPUCLK duty cycle is measured at 1.25V. DDCPU CY2277A Min. Typ. Max 2.5V 0.75 DDCPU = 3.3V 0.75 DDCPU = 3.3V ...
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... Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, V DDCPU Measured at 1.25V for 2.5V clocks Measured at 1.5V Measured at 1.5V Measured at 1.5V CPU, PCI, and SDRAM clock stabiliza- tion from power-up Rate of change of frequency CY2277A Min. Typ. Max 2.5V 0.60 4 ...
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... DDCPU Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks Measured at 1.5V CPU, PCI, and SDRAM clock stabiliza- tion from power-up Rate of change of frequency CY2277A Min. Typ. Max 2.5V 1.0 4.0 DDCPU = 3 ...
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... DDCPU Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks, V Measured at 1.25V for 2.5V clocks and at 1.5V for 3.3V clocks, V Measured at 1.5V CPU, PCI, and SDRAM clock stabiliza- tion from power-up Rate of change of frequency CY2277A Min. Typ. Max 2.5V 1.0 4.0 DDCPU = 3 ...
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... CPUCLK Outputs HIGH/LOW Time t 1C OUTPUT All Outputs Rise/Fall Time OUTPUT Document #: 38-07332 Rev. *A Description CY2277A Min. Max. Unit 0 100 kHz 250 300 ns 4.0 s Page ...
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... CPU-PCI Clock Skew CPUCLK PCICLK t 6 [13, 14] CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) Notes: 13. CPUCLK on and CPUCLK off latency CPUCLK cycles. 14. CPU_STOP may be applied asynchronously synchronized internally. Document #: 38-07332 Rev. *A CY2277A Page ...
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... Timing Requirements for the SMBus SDA t 11 SCL Notes: 15. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK. 16. PCI_STOP may be applied asynchronously synchronized internally. Document #: 38-07332 Rev CY2277A Page ...
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... If a Ferrite Bead is used F– tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Document #: 38-07332 Rev the loaded characteristic impedance trace from the clock generator V island. Ensure that the Ferrite Bead offers DD DD CY2277A of LOAD is the series terminating series Page ...
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... Note: All capacitors should be placed as close to each pin as possible. Ordering Information Ordering Code CY2277APVC-1 CY2277APAC-1M CY2277APVC-3 CY2277APAC-7M CY2277APVC-12 CY2277APAC-12M CY2277APVI-12 Intel and Pentium are registered trademarks of Intel Corporation. All product or company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07332 Rev DDQ3 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead Shrunk Small Outline Package O48 CY2277A 51-85061-C 51-85059-B ...
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... Document Title: CY2277A Pentium and 2 DIMMs or 3 SO-DIMMs Document Number: 38-07332 Issue REV. ECN NO. Date ** 111731 12/15/01 *A 121855 12/14/02 Document #: 38-07332 Rev. *A ® /II, 6x86, K6 Clock Synthesizer/Driver for Desktop/Mobile PCs with Intel Orig. of Change DSG Change from Spec number: 38-00612 to 38-07332 RBI Power up requirements added to Operating Conditions Information ...