CY23020LFI-1 Cypress Semiconductor Corporation., CY23020LFI-1 Datasheet

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CY23020LFI-1

Manufacturer Part Number
CY23020LFI-1
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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CY23020LFI-1
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Cypress Semiconductor Corporation
Document #: 38-07120 Rev. *B
Features
• 335 ps max Total Timing Budget™ (TTB)™ window
• 2.5V or 3.3V outputs
• 20 LVCMOS outputs
• 50 MHz to 200 MHz output frequency
• 50 MHz to 200 MHz input frequency
• Integrated phase-locked loop (PLL) with lock indicator
• Spread Aware™—designed to work with SSFTG
• 3.3V core power supply
• Available in 48-pin TSSOP and QFN packages
Block Diagram
RANGE
S1:2
reference signals
C1
MUL
1 0
1 2
1 1
FBIN
REF
4
5
6
7
8
9
1
2
3
V S S
C1
Q 1
V S S
Q 2
Q 3
V D D
Q 4
Q 5
Q 6
Q 7
Q 8
V D D
C1C1
4 8
1 3
Q
9
F
B
O
U
T
+
Output
Control
LOCKED
4 7
1 4
V
S
S
Logic
V
D
D
PLL
1 5
4 6
S
2
F
B
I
N
+
4 8 - p i n Q F N
1 6
4 5
S
1
Div
F
B
I
N
-
1 7
4 4
M
U
L
N
C
1 8
4 3
R
A
N
G
E
L
O
C
K
3901 North First Street
20-output, 200-MHz Zero Delay Buffer
Q19
Q1
Q2
Q17
Q18
FBOUT
4 2
1 9
V
D
D
C
G
N
D
4 1
C
1
2 0
V
S
S
C
2 1
4 0
V
D
D
C
R
E
F
-
Description
The CY23020-1-1 is a high-performance 200-MHz PLL-based
zero delay buffer designed for high-speed clock distribution
applications. The device features a guaranteed TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
The CY23020-1 outputs are three-state when S1 = S2 = 0 for
reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed
and the CY23020-1 functions as a fan-out buffer.
2 2
3 9
V
S
S
C
R
E
F
+
Pin Configurations
3 8
2 3
V
S
S
V
D
D
2 4
3 7
Q
1
9
Q
1
0
San Jose
V D D
V S S
V S S
Q 1 6
V D D
Q 1 8
Q 1 7
Q 1 5
Q 1 4
Q 1 3
Q 1 2
Q 1 1
2 7
3 3
3 2
3 1
2 8
2 5
3 6
3 5
3 4
3 0
2 9
2 6
RANGE
FBOUT
FBIN–
FBIN+
LOCK
CA 95134
GND
GND
GND
VDD
MUL
VDD
VDD
NC
Q5
Q6
Q7
Q8
Q9
Q1
Q2
Q3
Q4
S2
S1
Revised November 5, 2002
48-pin TSSOP
13
14
15
16
17
18
19
20
21
22
23
24
10
12
11
1
2
3
4
5
6
7
8
9
CY23020-1
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
408-943-2600
Q14
GND
Q13
Q12
VDD
Q11
Q10
GND
GNDC
VDDC
C1
GND
VDDC
GNDC
REF–
REF+
VDD
Q19
Q18
GND
Q17
Q16
VDD
Q15
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CY23020LFI-1 Summary of contents

Page 1

Features • 335 ps max Total Timing Budget™ (TTB)™ window • 2.5V or 3.3V outputs • 20 LVCMOS outputs • 50 MHz to 200 MHz output frequency • 50 MHz to 200 MHz input frequency • Integrated phase-locked loop (PLL) ...

Page 2

Pin Definitions Pin No. Pin Name TSSOP QFN REF REF– FBIN FBIN– FBOUT 6 48 Q1: 10, 12, 1,3,4,6,7,9,1 13, 15, 16, 0,12,13,24,2 18, 19, 30, 5,27,28,30,3 31, 33, ...

Page 3

Table 1. Output Configuration source 0 0 Three-state 0 1 Reserved 1 0 Reference input 1 1 PLL output Table 2. Frequency Range Setting Range Output Frequency Range 0 50–100 MHz 1 100–200 MHz Table 3. Output ...

Page 4

C byp The CY23020-1 uses a differential input receiver to increase it’s rejection of common mode input noise and thus increase device performance. To ensure that any noise appears equally on both the REF– and REF+ pins, ...

Page 5

Absolute Maximum Ratings Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other condi- Parameter V Voltage on any V ...

Page 6

Full Swing AC Electrical Characteristics Load: (See term. diagram pF) TSSOP Package L Parameter Description Input Frequency F IN Output Frequency F OUT Input Slew Rate (+ or –) t ISR Output Rise Rate t R Output ...

Page 7

Full Swing AC Electrical Characteristics Load: (See term. diagram pf) QFN Package L Parameter Description F Input Frequency IN F Output Frequency OUT t Input Slew Rate (+ or –) ISR t Output Rise Rate R t ...

Page 8

... CY23020ZC–1 48-pin TSSOP CY23020ZC–1T 48-pin TSSOP—Tape and Reel CY23020LFI–1 48- pin QFN CY23020LFI–1T 48-pin QFN—Tape and Reel Package Diagrams 48-Lead Thin Shrunk Small Outline Package, Type × 12 mm) Z48 Note: 5. Theta J = 95° C/W for TSSOP package. ...

Page 9

Package Diagrams (continued) Spread Aware, Total Timing Budget, and TTB are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07120 Rev. *B © Cypress Semiconductor Corporation, ...

Page 10

Document Title: CY23020-1 20-output, 200-MHz Zero Delay Buffer Document Number: 38-07120 REV. ECN No. Issue Date ** 109287 10/30/01 *A 113758 07/22/02 *B 118945 11/06/02 Document #: 38-07120 Rev. *B Orig. of Change Description of Change SZV New Data Sheet ...

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