CY7C144V-25AI Cypress Semiconductor Corporation., CY7C144V-25AI Datasheet
CY7C144V-25AI
Related parts for CY7C144V-25AI
CY7C144V-25AI Summary of contents
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Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 4K/8K/16K/32K x 8 organizations (CY7C0138V/144V/ 006V/007V) • 4K/8K/16K/32K x 9 organizations (CY7C0139V/145V/ 016V/017V) • 0.35-micron CMOS for optimum speed/power [1] • High-speed ...
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Functional Description The CY7C138V/144V/006V/007V and CY7C139V/145V/ 016V/017V are low-power CMOS 4K, 8K, 16K, and 32K x8/9 dual-port static RAMs. Various arbitration schemes are includ the devices to handle situations when multiple proces- sors access the same piece of ...
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... CY7C144V ( CY7C145V ( 2728 29 30 3132 64-Pin TQFP Top View CY7C144V ( CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V ...
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Pin Configurations (continued) NC I/O 2L I/O 3L I/O 4L I/O 5L GND I GND I/O 0R I I/O 3R I/O 4R I ...
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Pin Configurations (continued) I/O 2L I/O 3L I/O 4L I/O 5L GND I GND I/O 0R I I/O 3R I/O 4R I/O 5R I/O6 R I/O 2L I/O 3L I/O ...
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Selection Guide CY7C138V/144V/006V/007V CY7C139V/145V/016V/017V Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I SB1 (mA) (Both Ports TTL level) Typical Standby Current for I SB3 ( A) (Both Ports CMOS level) Shaded areas contain advance information. ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage ( Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Output Leakage Current OZ I Operating Current (V = ...
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Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [15 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range Parameter Description [21] t BUSY HIGH to Data Valid BDD [20] INTERRUPT TIMING t INT Set Time INS t INT Reset Time INR SEMAPHORE TIMING t SEM Flag Update Pulse (OE or SEM) SOP ...
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Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No .2 (Either Port CE/OE Access DATA OUT I CC CURRENT I SB [23, 25, 26, ...
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Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32 R/W NOTE 34 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [32 R/W DATA IN Notes: 28. ...
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Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...
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Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 40 LOW. ...
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Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No.2 (Address Arbitration) Left ...
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Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFF (See Functional Description R/W L INT R [43] t INS Right Side Clears INT : R ADDRESS R/W R ...
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... CY7C006V/16V, 7FFF for the CY7C007V/17V) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C138V/9V, 1FFE for the CY7C144V/5V, 3FFE for the CY7C006V/16V, 7FFE for the CY7C007V/17V) is the mailbox for the left port. When one port writes to the other port’ ...
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Table 1. Non-Contending Read/Write Inputs CE R/W OE SEM High Data Out High Data Data Out L L ...
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... Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C144V-15AC CY7C144V-15JC 20 CY7C144V–20AC CY7C144V–20JC CY7C144V–20AI CY7C144V–20JI 25 CY7C144V–25AC CY7C144V–25JC CY7C144V–25AI CY7C144V–25JI Shaded areas contain advance information. PRELIMINARY 68-Pin PLCC ...
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Ordering Information (continued 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C145V-15JC 20 CY7C145V–20JC CY7C145V–20JI 25 CY7C145V–25JC CY7C145V–25JI Shaded areas contain advance information. 16K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C006V-15AC ...
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Ordering Information (continued) 32K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C017V-15JC 20 CY7C017V–20JC CY7C017V–20JI 25 CY7C017V–25JC CY7C017V–25JI Shaded areas contain advance information. Document #: 38–00677–B Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x ...
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Package Diagrams (continued) © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor ...
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... POR circuit is at fault. Applicable devices—All speed/package/temperature combi- nations of the following: • CY7C138V • CY7C139V • CY7C144V • CY7C145V • CY7C006V • CY7C016V • CY7C007V • CY7C017V Cypress design change—Cypress design team has identified the root cause ...