ISPLSI3448-90LB432 Lattice Semiconductor Corp., ISPLSI3448-90LB432 Datasheet
ISPLSI3448-90LB432
Specifications of ISPLSI3448-90LB432
Related parts for ISPLSI3448-90LB432
ISPLSI3448-90LB432 Summary of contents
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... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 3448 Functional Block Diagram Input Bus TOE Output Routing Pool I I/O 2 I/O 3 I I/O 6 I/O 7 I/O 8 ...
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Description (continued) All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 224 I/O cells, each of which is ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load conditions (See Figure 2) TEST CONDITION A 470 ...
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External Switching Characteristics 5 TEST 2 PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 24 I/O Register Bypass iobp t 25 I/O Latch Delay iolat t 26 I/O Register Setup Time before Clock iosu t 27 I/O Register Hold Time after Clock ioh t 28 I/O ...
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Internal Timing Parameters 2 PARAMETER # Outputs t 47 Output Buffer Delay Output Buffer Delay, Slew Limited Adder obs t 49 I/O Cell OE to Output Enabled oen t 50 I/O Cell OE to Output Disabled odis ...
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Timing Model I/O Cell I/O Reg Bypass I/O #24 (Input) Input Register Q D RST #53 # Reset Y3,4 #52 Y0,1,2 GOE0,1 TOE Derivations of su, h and co from the Product Term ...
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Power Consumption Power consumption in the ispLSI 3448 device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3. Typical Device Power Consumption vs fmax I CC can ...
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Signal Description Signal Name I/O Input/Output – These are the general purpose I/O used by the logic array. GOE0, GOE1 Global Output Enable inputs. TOE Test Output Enable pin – This pin tristates all I/O pins when a logic low ...
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I/O Locations Signal BGA Signal BGA I/O 0 T30 I/O 38 AK24 I/O 1 U29 I/O 39 AL24 I/O 2 U31 I/O 40 AJ23 I/O 3 V31 I/O 41 AL23 I/O 4 W31 I/O 42 AJ22 I/O 5 W29 I/O ...
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Signal Configuration ispLSI 3448 432-Ball BGA Signal Diagram I/O I/O I/O I/O I/O I/O A GND GND VCC ...
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Part Number Description ispLSI 3448 Device Family Device Number Speed MHz max MHz max Ordering Information FAMILY fmax (MHz) tpd (ns) 90 ispLSI 70 Specifications ispLSI 3448 – XXXX COMMERCIAL ...