HD4074629TF Renesas Electronics Corporation., HD4074629TF Datasheet
HD4074629TF
Related parts for HD4074629TF
HD4074629TF Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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AS Microcomputer Incorporating a DTMF Generator Circuit Description The HD404629R Series is part of the HMCS400-Series microcomputers designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has a high precision dual- tone multifrequency (DTMF) generator, LCD controller/driver, ...
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HD404629R Series Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode One external input for transition from stop mode to active mode Instruction cycle time (min.): Operation voltage 6.0 ...
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... HD404628RFS HD404628RTF HD4046212RH 12,288 HD4046212RFS HD4046212RTF HD404629RH 16,384 HD404629RFS HD404629RTF HD4074629H 16,384 HD4074629FS HD4074629TF TM HD404629R Series Package 100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B) 100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP ...
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HD404629R Series List of Functions Product name ROM (Words) RAM (Digits) I/O Large-current I/O pins LCD segment multiplexed pins Timer / Counter Input capture Timer output Event input Serial interface DTMF generation circuit A/D converter LCD controller / driver circuit ...
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Pin Arrangement TEST 7 OSC 8 1 OSC 9 2 RESET GND ...
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HD404629R Series Pin Arrangement TONER ref TEST 9 OSC 10 1 OSC 11 2 RESET ...
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Pin Description Pin Number FP-100B Item Symbol TFP-100B Power supply GND 13 TEST Test 7 Reset RESET 10 Oscillato OSC OSC Port D –D 14– ...
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HD404629R Series Pin Number FP-100B Item Symbol TFP-100B A converter –AN 2– DTMF TONER 99 TONEC 98 VT 100 ref 8 FP-100A I/O Function 3 Power pin for A/D converter: Connect ...
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Block Diagram INT 0 INT 1 INT 2 INT 3 INT 4 EVNB TOB TOC EVND TOD SCK ref TONER TONEC ...
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HD404629R Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. ROM address $0000 Vector address (16 words) $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 HD404628R ...
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RAM Memory Map The MCU contains a 1,876-digit a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped ...
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HD404629R Series RAM address $000 RAM-mapped register area $040 Memory registers (10 digits) $050 LCD display area (52 digits) $084 $090 $260 $3C0 $3FF Data (464 digits) (464 digits (bank = 0) Notes: 1. The data area ...
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Bit 3 Bit 2 IM0 IF0 $000 (IM of INT (IF of INT ) 0 IMTA IFTA $001 (IM of timer A) (IF of timer A) IMTC IFTC $002 (IM of timer C) (IF of timer C) IMAD IFAD $003 ...
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HD404629R Series RAM address Bit 3 $000 $003 PMRA $004 Not used SMRA $005 R2 /SCK 1 SRL $006 SRU $007 TMA $008 * 1 * TMB1 $009 2 TRBL/TWBL $00A TRBU/TWBU $00B * MIS $00C TMCI ...
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Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. Memory registers $040 MR(0) $3C0 MR(1) $041 MR(2) $042 MR(3) $043 MR(4) ...
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HD404629R Series LCD Data Area ($050–$083): Used for storing 52-digit LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to the LCD description for details. ...
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Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. Accumulator B register W register X register Y register SPX register SPY register Carry Status ...
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HD404629R Series SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA 1-bit flag that stores ALU overflow generated by an ...
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Table 1 Initial Values After MCU Reset Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag flags/mask Interrupt request flag Interrupt mask I/O Port data register Data control register Port mode register A Port mode register B Port ...
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HD404629R Series Table 1 Initial Values After MCU Reset (cont) Item Timer/ Timer write register B counters, serial Timer write register C interface Timer write register D Octal counter A/D A/D mode register A/D data register LCD LCD control register ...
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Item Abbr. Carry flag (CA) Accumulator (A) B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) Serial data register (SRL, SRU) RAM RAM enable flag (RAME) Port mode (PMRC2) register C bit 2 System clock (SSR3) select ...
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HD404629R Series during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address ...
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IE $ 000,2 IFO INT interrupt 0 $ 000,3 IMO $ 001,0 INT IF1 interrupt 1 $ 001,1 IM1 $ 001,2 Timer A interrupt IFTA $ 001,3 IMTA $ 002,0 Timer B interrupt IFTB $ 002,1 IMTB $ ...
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HD404629R Series Table 3 Interrupt Processing and Activation Conditions Interrupt INT INT Cuntrol Bit IF0 . IM0 1 0 IF1 . IM1 * 1 IFTA . IMTA * * IFTB . IMTB * * + IF2 ...
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Power on No RESET = 1? Yes Execute instruction Reset MCU Figure 11 Interrupt Processing Flowchart HD404629R Series Yes Interrupt request Accept interrupt (PC Stack ...
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HD404629R Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit ...
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Detection edge selection register 2 (ESR2: $027) Bit 3 2 Initial value 0 0 Read/Write W W Bit name ESR23 ESR22 ESR23 ESR22 EVND detection edge detection 1 Falling-edge detection 1 0 Rising-edge detection 1 Double-edge detection ...
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HD404629R Series Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3) IMTA Interrupt ...
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Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12. Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3) IMTC Interrupt Request 0 ...
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HD404629R Series Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 16. Table 16 Serial Interrupt Mask (IMS: $023, Bit 3) IMS Interrupt Request 0 Enabled ...
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Operating Modes The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables 20 and 21. Transitions between operating modes are shown in figure 14. Active Mode: All MCU functions operate ...
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HD404629R Series Table 20 Operations in Low-Power Dissipation Modes Function Stop Mode CPU Reset RAM Retained Timer A Reset Timer B Reset Timer C Reset Timer D Reset Serial interface Reset A/D Reset LCD Reset DTMF Reset *1 I/O Reset ...
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Standby mode f : Oscillate OSC SBY f : Oscillate X : Stop ø CPU Interrupt : f ø cyc CLK ø cyc PER f : Oscillate OSC SBY f : Oscillate X : Stop ø CPU Interrupt ...
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HD404629R Series Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the port status, ...
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Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC oscillator to operate or stop can be selected by setting bit ...
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HD404629R Series Subactive Mode: The OSC and OSC 1 the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The ...
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Active mode Interrupt strobe INT 0 Interrupt request generation (During the transition from watch mode to active mode only) Note: If the time from the fall of the INT and active mode is entered is designated Tx, then Tx will ...
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HD404629R Series Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: Set LSON to ...
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Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, ...
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HD404629R Series Low-power mode operation cycle IF: Interrupt request flag IM: Interrupt mask IE: Interrupt enable flag PC: Program counter CA: Carry flag ST: Status flag Figure 21 MCU Operating Sequence (MCU Operation Cycle) 40 MCU operation cycle Yes IF ...
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STOP/SBY instruction and Yes Interrupt service routine Yes Hardware NOP execution PC (PC)+1 MCU operation cycle * Note: Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF ...
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HD404629R Series Notes: 1. When watch or subactive mode on HD404629R Series/HD4074629 is used and the LCD function is off in that mode, the watch mode or subactive mode current is larger, and consequently the following settings should be made. ...
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Notes: 2. When the MCU is in watch mode or subactive mode, if the high level period before the falling edge shorter than the interrupt frame period after the falling edge of I ...
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HD404629R Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 26. As shown in table 22, a ceramic oscillator can be connected to OSC X2. The system oscillator can also be operated by ...
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System clock select register (SSR: $029) Bit 3 2 Initial value 0 0 Read/Write W W Bit name SSR3 SSR2 SSR3 32-kHz oscillation stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode 32-kHz oscillation division SSR2 ...
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HD404629R Series Table 22 Oscillator Circuit Examples Circuit Configuration External clock External operation oscillator Open Ceramic oscillator (OSC 1 , OSC 2 ) Ceramic oscillator GND C Crystal oscillator 1 (OSC 1 , OSC ) 2 Crystal oscillator C 2 ...
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Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC ...
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HD404629R Series V CC Pull-up MOS Table 24 Circuit Configurations of I/O Pins I/O Pin Type Circuit Input/output pins Input pins 48 Pull-up control signal V CC Buffer control signal Input data Input control signal Figure 29 I/O Buffer Configuration ...
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Table 24 Circuit Configurations of I/O Pins (cont) I/O Pin Type Peripheral Input/output function pins pins Output pins Input pins Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, ...
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HD404629R Series D Port (D –D ): Consist of 10 input/output pins and 2 input pins addressed by one bit current I/O pins, and D and D 10 Pins D –D are set by the SED and ...
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Data control register DCD0, DCD1 Bit Initial value Read/Write Bit name DCD2 Bit Initial value Read/Write Bit name DCR0 to DCR7 Bit Initial value Read/Write Bit name All Bits 0 1 Correspondence between ports and DCD/DCR bits Register Name Bit ...
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HD404629R Series Port mode register C (PMRC: $025) Bit 3 Initial value 0 Read/Write W Bit name PMRC3 PMRC3 D /INT INT 1 0 PMRC2 D /STOPC mode selection STOPC 1 ...
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Timer mode register B2 (TMB2: $013) Bit 3 2 Initial value — — Read/Write — — Bit name Not used Not used TMB21 TMB20 R1 /TOB mode selection TOB 1 0 TOB 1 TOB ...
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HD404629R Series Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name TMD23 TMD22 Don’t care Figure 35 Timer Mode Register D2 (TMD2) Serial mode register A (SMRA: $005) Bit 3 Initial value 0 Read/Write ...
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Port mode register A (PMRA: $004) Bit 3 2 Initial value — — Read/Write — — Bit name Not used Not used PMRA1 R2 /SI mode selection Figure 37 Port Mode Register A (PMRA) ...
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HD404629R Series LCD output register 2 (LOR2: $01E) Bit Initial value Read/Write Bit name LOR23 LOR23 R4 /SEG8 mode selection SEG8 LOR22 R4 /SEG7 mode selection SEG7 LCD output register ...
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Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can ...
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HD404629R Series Prescalers The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 25, and the prescalers output supply is shown in figure 42. The timers A–D input clocks except external events, ...
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Timers The MCU has four timer/counters (A to D). Timer A: Free-running timer Timer B: Multifunction timer Timer C: Multifunction timer Timer D: Multifunction timer Timer 8-bit free-running timer. Timers B–D are 8-bit multifunction timers, whose functions ...
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HD404629R Series 32.768-kHz 1/4 oscillator 1/2 tw ø System PER clock Data bus Clock line Signal line Timer A Operations: Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A ...
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Timer mode register A (TMA: $008) Bit 3 Initial value 0 Read/Write W Bit name TMA3 TMA2 TMA3 TMA2 TMA1 TMA0 ...
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HD404629R Series The block diagram of timer B is shown in figure 45. Timer output TOB control logic EVNB System PER clock 2 Timer output control Data bus Clock line Signal line 62 Timer read register ...
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Timer B Operations: Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, ...
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HD404629R Series Toggle output waveform (timers B, C, and D) Free-running timer Reload timer PWM output waveform (timers C and D) TMC13 = 0 TMD13 = 0 TMC13 = 1 TMD13 = 1 64 256 clock cycles 256 clock cycles ...
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Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register ...
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HD404629R Series Timer mode register B2 (TMB2: $013) Bit 3 2 Initial value — — Read/Write — — Bit name Not used Not used Figure 48 Timer Mode Register B2 (TMB2) Timer mode register B2 (TMB2: $013): Two-bit read/write register ...
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The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by ...
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HD404629R Series Timer C Timer C Functions: Timer C has the following functions. Free-running/reload timer Watchdog timer Timer output operation (toggle and PWM outputs) The block diagram of timer C is shown in figure 54. Watchdog on TOC ...
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Timer C Operations: Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, ...
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HD404629R Series Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer ...
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Timer mode register C2 (TMC2: $014) Bit 3 2 Initial value — 0 Read/Write — R/W Bit name Not used TMC22 TMC22 Figure 56 Timer Mode Register C2 (TMC2) Timer write register C (lower digit) (TWCL: $00E) Bit Initial value ...
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HD404629R Series Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name Figure 59 Timer Read Register C Lower Digit (TRCL) Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name Figure ...
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Timer D Timer D Functions: Timer D has the following functions. Free-running/reload timer External event counter Timer output operation (toggle and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown ...
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HD404629R Series 1 output: The operation is basically the same as that of timer-B’s 1 output. PWM output: The operation is basically the same as that of timer-C’s PWM output. Input capture timer operation: The input capture timer counts the ...
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EVND Edge detection logic øPER System clock 128 512 2048 2 Edge detection control Data bus Clock line Signal line TOD Figure 61 Block Diagram of Timer D (Free-Running/Reload Timer) Timer read register DL (TRDL) 4 ...
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HD404629R Series EVND Edge detection logic øPER System clock 2 Edge detection control Figure 62 Block Diagram of Timer D (Input Capture Timer) Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and ...
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Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure ...
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HD404629R Series Port mode register C (PMRC: $025): Write-only register that selects R2 in figure 53 reset MCU reset. Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals ...
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Timer write register D (upper digit) (TWDU: $012) Bit 3 Initial value Undefined Undefined Read/Write W Bit name TWDU3 TWDU2 Figure 66 Timer Write Register D Upper Digit (TWDU) Timer read register D (lower digit) (TRDL: $011) Bit 3 Initial ...
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HD404629R Series Detection edge register 2 (ESR2: $027) Bit 3 Initial value 0 Read/Write W Bit name ESR23 ESR23 ESR22 EVND detection edge detection 1 Falling-edge detection 0 Rising-edge detection 1 1 Double-edge detection Note: Both falling ...
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Note on Use When using the timer output as PWM output, note the following point. From the update of the timer write register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, ...
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HD404629R Series Serial Interfaces The serial interface serially transfers and receives 8-bit data, and includes the following features. Multiple transmit clock sources External clock Internal prescaler output clock System clock Output level control in idle states Five registers, an octal ...
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SO Idle control logic SCK I/O control logic SI ø System PER clock 128 512 2048 Data bus Clock line Signal line Figure 70 Block Diagram of Serial Interface HD404629R Series Serial interrupt Octal counter request flag ...
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HD404629R Series Serial Interface Operation Selecting and Changing the Operating Mode: Table 28 lists the serial interface’s operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register ...
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Table 29 Serial Transmit Clock (Prescaler Output) SMRB SMRA Bit 0 Bit 2 Bit Operating States: The serial interface has the following operating states; transitions between them ...
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HD404629R Series In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag ...
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State STS wait state MCU reset Port selection PMRA write External clock selection SMRA write Output level control in SMRB write SRL, SRU write STS instruction SCK pin (input) Undefined SO pin IFS State STS wait state MCU reset Port ...
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HD404629R Series Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be ...
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Transmit clock error detection flowchart Transmit clock wait state State SCK pin (input) 1 SMRA write IFS Figure 73 Transmit Clock Error Detection Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMRA write Yes IFS = 1? No Normal termination ...
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HD404629R Series If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and ...
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Serial mode register A (SMRA: $005) Bit 3 Initial value 0 Read/Write W Bit name SMRA3 SMRA2 R2 /SCK 1 SMRA3 mode selection SCK Figure 74 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: ...
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HD404629R Series Serial mode register B (SMRB: $028) Bit 3 Initial value — Read/Write — Bit name Not used SMRB1 Output level control in idle states 0 Low level 1 High level Figure 75 Serial Mode Register B (SMRB) Serial ...
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Serial data register (upper digit) (SRU: $007) Bit Initial value Read/Write Bit name Transmit clock Serial output data Serial input data latch timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 79). R2 /SI pin ...
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HD404629R Series Miscellaneous Register (MIS: $00C): This register has the following function (figure 80). R2 /SO pin PMOS control 3 Miscellaneous register (MIS: $00C 4-bit write-only register and is reset MCU reset. Miscellaneous register (MIS: ...
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Off in stop, watch, and subactive modes Resistance ladder Data bus Signal line Figure 81 Block Diagram of A/D Converter A/D Mode Register (AMR: $016): Four-bit write-only register ...
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HD404629R Series A/D mode register (AMR: $016) Bit 3 Initial value 0 Read/Write W Bit name AMR3 AMR3 AMR2 Analog input selection A/D Data Register (ADRL: $017, ADRU: ...
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A/D data register (lower digit) (ADRL: $017) Bit Initial value Read/Write Bit name Figure 84 A/D Data Register Lower Digit (ADRL) A/D data register (upper digit) (ADRU: $018) Bit Initial value Read/Write Bit name Figure 85 A/D Data Register Upper ...
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HD404629R Series Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read ...
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Sine wave TONER counter D/A VT ref Sine wave TONEC counter D/A TONEC output control f 400 kHz OSC 800 kHz 1/2 2 MHz 1/5 4 MHz 1/10 Data bus Clock line Signal line Figure 88 Block Diagram of DTMF ...
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HD404629R Series Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output frequencies as shown in figure 89, and is reset MCU reset. Tone generator mode register (TGM: $019) Bit 3 Initial value 0 Read/Write ...
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System Clock Select Register (SSR: $029): Four-bit write-only register. This register must be set to the value specified in figure 91 depending on the frequency of the oscillator connected to the OSC pins. Note that if the combination of the ...
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HD404629R Series DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER, TONEC) transmit the sine waves of the row-group and ...
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VT ref GND Figure 93 Waveform of Tone ...
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HD404629R Series LCD Controller/Driver The MCU has an LCD controller and driver which drive 4 common signal pins and 52 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR: ...
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LCD Data Area and Segment Data ($050–$083): As shown in figure 95, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle ...
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HD404629R Series LCD Control Register (LCR: $01B): Three-bit write-only register which controls LCD blanking, on/off switching of the liquid-crystal display’s power supply division resistor, and display in watch and subactive modes, as shown in figure 96. Blank/display Blank: Segment signals ...
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LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in figure 97. frequency on duty cycle is listed in table 31. LCD duty cycle/clock control register (LMR: $01C) ...
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HD404629R Series Table 31 LCD Frame Frequencies for Different Duty Cycles Duty Cycle LMR3 LMR2 Static ...
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LCD Output Register 1 (LOR1: $01D): Write-only register used to specify ports R3 SEG4 by individual pins (figure 98). LCD output register 1 (LOR1: $01D) Bit Initial value Read/Write Bit name LOR13 LOR13 R3 /SEG4 mode selection ...
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HD404629R Series LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R5–R7 as pins SEG9– SEG20 in 4-pin units (figure 100). LCD output register 3 (LOR3: $01F) Bit 3 2 Initial value — 0 Read/Write — W ...
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GND LCD LCD LCD LCD V V GND CC LCD Figure 101 LCD Connection Examples R ...
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HD404629R Series TM ZTAT Microcomputer with Built-in programmable ROM Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, ...
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Table 32 Selection of Mode Mode Writing Verification Prohibition of programming Table 33 PROM Writer Program Address ROM size 8k 12k 16k “Low” “High” V “High” “Low” V “High” “High” V Address $0000~$3FFF $0000~$5FFF $0000~$7FFF HD404629R Series ...
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HD404629R Series Programmable ROM (HD4074629) The HD4074629 is a ZTAT mode. PROM Mode Pin Description Pin No. MCU Mode FP-100B FP-100A Pin TFP-100B Name ...
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PROM Mode Pin Description (cont) Pin No. MCU Mode FP-100B FP-100A Pin TFP-100B Name /SEG10 I /SEG11 I /SEG12 I /SEG13 I ...
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HD404629R Series PROM Mode Pin Functions V : Applies the programming voltage (12 the built-in PROM. PP CE: Inputs a control signal to enable PROM programming and verification Inputs a data output control signal ...
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Set programming/verification modes V PP Yes No n < 25 Fail Figure 103 Flowchart of High-Speed Programming Start = 12.5 0 6.0 0. Address = ...
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HD404629R Series Programming Electrical Characteristics DC Characteristics ( specified) Item Symbol Pin(s) Input high OE, CE voltage level Input low OE, CE voltage level Output high voltage ...
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Input pulse level: 0 2.2 V Input rise/fall time Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Address t AS Data Data in Stable ...
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HD404629R Series Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTAT™ microcomputer is the same as an EPROM cell programmed by applying a high voltage between its control gate and drain to inject hot ...
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PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that ...
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HD404629R Series Addressing Modes RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 107 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are ...
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ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 108 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the ...
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HD404629R Series 1st word of instruction [JMPL] [BRL] Opcode [CALL] Program counter Program counter Program counter Opcode [TBR] Program counter 124 ...
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Instruction Opcode [P] 0 Referenced ROM address RA 13 ROM data RO 9 Accumulator, B register ROM data RO 9 Output registers R1 ...
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HD404629R Series Figure 110 Branching when the Branch Destination Page Boundary 126 256 (n – 255 BR AAA 256n AAA NOP BR AAA 256n + 254 BR BBB 256n + 255 256 ( ...
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Instruction Set The MCU has 101 instructions, classified into the following 10 groups: Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions The functions ...
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HD404629R Series Table 35 Register-Register Instructions Operation Mnemonic Load A LAB from B Load B LBA from A Load A LAW* from W Load A LAY from Y Load A LASPX from SPX Load A LASPY from SPY Load A ...
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Table 36 RAM Address Instructions Operation Mnemonic Load W from LWI i immediate Load X from LXI i immediate Load Y from LYI i immediate Load W LWA from A Load X LXA from A Load Y LYA from A ...
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HD404629R Series Table 37 RAM Register Instructions Operation Mnemonic Load A from LAM memory LAMX LAMY LAMXY Load A from LAMD d memory Load B from LBM memory LBMX LBMY LBMXY Load memory LMA from A LMAX LMAY LMAXY Load ...
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Table 37 RAM Register Instructions (cont) Operation Mnemonic Load memory LMAIY from A, increment Y LMAIYX Load memory LMADY from A, decrement Y LMADYX Exchange XMA memory and A XMAX XMAY XMAXY Exchange XMAD d memory and A Exchange XMB ...
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HD404629R Series Table 38 Arithmetic Instructions Operation Mnemonic Operation Code Add immediate Increment B IB Decrement B DB Decimal DAA adjust for addition Decimal DAS adjust for subtraction Negate A NEGA Complement COMB B Rotate right ...
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Table 38 Arithmetic Instructions (cont) Operation Mnemonic AND memory ANM with A AND memory ANMD d with A OR memory ORM with A OR memory ORMD d with A EOR memory EORM with A EOR memory EORMD d with A ...
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HD404629R Series Table 39 Compare Instructions Operation Mnemonic Immediate not INEM i equal to memory Immediate not INEMD i, d equal to memory A not equal to ANEM memory A not equal to ANEMD d memory B not equal to ...
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Table 40 RAM Bit Manipulation Instructions Operation Mnemonic Set memory bit SEM n Set memory bit SEMD n,d Reset memory REM n bit Reset memory REMD n,d bit Test memory bit TM n Test memory bit TM n,d Table 41 ...
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HD404629R Series Table 42 Input/Output Instructions Operation Mnemonic Set discrete SED I/O latch Set discrete SEDD m I/O latch direct Reset RED discrete I/O latch Reset REDD m discrete I/O latch direct Test discrete I/O TD latch Test discrete I/O ...
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Table 40 Control Instructions Operation Mnemonic No operation NOP Start serial STS Standby SBY mode/Watch mode* Stop mode/ STOP Watch mode Note: * Only on return from subactive mode. Operation Code ...
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HD404629R Series Table 44 Opcode Map NOP XSPX XSPY XSPXY ANEM 1 RTN RTNI LBM(XY) 5 LMAIY(X) 6 NEGA XMA(XY) 9 LAM(XY) A ROTR ROTL ...
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Table 44 Opcode Map (cont LAW 1 LWA COMB XMAD 9 LAMD ...
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HD404629R Series Absolute Maximum Ratings Item Supply voltage Programming voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Maximum output current Operating temperature Storage temperature Notes: Permanent damage may occur if these absolute maximum ratings ...
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Electrical Characteristics DC Characteristics (HD404628R, HD4046212R, HD404629R – +75 C; HD4074629 unless otherwise specified) Item Symbol Pin(s) Input high V RESET, SCK, IH voltage SI, INT INT INT EVNB, EVND OSC Input low ...
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HD404629R Series DC Characteristics (HD404628R, HD4046212R, HD404629R – +75 C; HD4074629 unless otherwise specified) (cont) Item Symbol Pin(s) Current I V SUB CC dissipation in subactive mode Current I V WTC1 CC dissipation ...
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I/O Characteristics for Standard Pins (HD404628R, HD4046212R, HD404629R: V GND = – +75 C; HD4074629 unless otherwise specified) Item Symbol Pin(s) Input high voltage R0–R7 Input ...
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HD404629R Series I/O Characteristics for High-Current Pins (HD404628R, HD4046212R, HD404629R: V 6.0 V, GND = – +75 C; HD4074629 +75 C, unless otherwise specified) Item Symbol Pin(s) Input high V D –D ...
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DTMF Characteristics (HD404628R, HD4046212R, HD404629R – +75 C; HD4074629 otherwise specified) Item Symbol Tone output V OR voltage (1) Tone output V OC voltage (2) Tone output % DIS distortion Tone output dB ...
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HD404629R Series A/D Converter Characteristics (HD404628R, HD4046212R, HD404629R: V GND = – +75 C; HD4074629 unless otherwise specified) Item Symbol Pin(s) Analog power voltage Analog input ...
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AC Characteristics (HD404628R, HD4046212R, HD404629R – +75 C; HD4074629 unless otherwise specified) Item Symbol Pin(s) Clock oscillation f OSC OSC frequency X1, X2 Instruction cycle t — cyc time t — subcyc Oscillation ...
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HD404629R Series AC Characteristics (HD404628R, HD4046212R, HD404629R: V – +75 C; HD4074629: V specified) (cont) Item Symbol External clock t CPf fall time INT , EVNB , –INT EVND high widths INT , ...
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Serial Interface Timing Characteristics (HD404628R, HD4046212R, HD404629R: V GND = – +75 C; HD4074629 unless otherwise specified) During Transmit Clock Output Item Symbol Transmit clock cycle time t Scyc Transmit clock high ...
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HD404629R Series Figure 112 Distortion and dB INT EVNB, EVND 150 R = 100 k L TONEC R = 100 k L TONER GND Figure 111 Tone Output Load Circuit R = 100 k L GND CR OSC 1 1/f ...
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RESET 0.9V 0.1V Figure 115 Reset Timing STOPC 0.9V Figure 116 STOPC Timing t SCKf SCK V – 1.0 V (0. 0.4 V (0. DSO SO SI Note: V – 1.0 V ...
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HD404629R Series Test point 152 1S2074 equivalent Figure 118 Timing Load Circuit = 2 ...
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Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404629R). A 16-kword data size ...
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HD404629R Series HD404628R/HD4046212R/ HD404629R Option List Please check off the appropriate applications and enter the necessary information. Date of order / / Customer Department Name ROM code name LSI number (Hitachi entry) 1. ROM Size HD404628R 8-kword HD4046212R 12-kword HD404629R ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...