M32171F4VFP Renesas Electronics Corporation., M32171F4VFP Datasheet
M32171F4VFP
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M32171F4VFP Summary of contents
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REJ09B0015-0200Z 32 RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER Before using this material, please visit our website to confirm that this is the most current document available. Rev. 2.00 Revision date: Sep 19, 2003 32171 Group User’s Manual M32R FAMILY / M32R/ECU ...
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Keep safety first in your circuit designs! Renesas Technology Corporation puts the maximum effort into making semiconductor prod- • ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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REVISION HISTORY Rev. Date Page 0.1 – First edition issued Apr 8, 2000 1.0 Nov 1, 2002 all Explanation of the M32171F2 added all Designation of M32R/E changed to M32R/ECU P1-6 Description in Section 1.1.6, Built-in Full-CAN Function, corrected Incorrect: ...
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REVISION HISTORY Rev. Date Page 1.0 Nov 1, 2002 P6-27 Table 6.5.5, “M32171F2’s relevant block and specificaion address,” added P6-30 Table 6.5.9, “Block configuration of M32171F2 flash memory,” added P6-38 Figure 6.5.15, Figure 6.5.16 and Figure 6.5.17 corrected P6-40 (3) ...
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REVISION HISTORY Rev. Date Page 1.0 Nov 1, 2002 P10-84 Port numbers added to Figure 10.4.1 P10-93 Port numbers added to Figure 10.4.5 P10-96 Port numbers added to Figure 10.4.6 P10-124 Port numbers added to Figure 10.5.1 P10-130 Figure 10.5.3 ...
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REVISION HISTORY Rev. Date Page 1.0 P13-28 Figure 13.2.5 corrected Nov 1, 2002 P13-29 Figure 13.2.6 corrected P13-30 Figure 13.2.7 corrected P13-35 Figure 13.2.8, “Relationship between Mask Registers and the Controlled Slots,” added Figure 13.2.9, “ Operation of the Acceptance ...
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REVISION HISTORY Rev. Date Page 1.0 Nov 1, 2002 P21-7 (3) Electrical characteristics when f(XIN MHz corrected P21-10 Section 21.1.4, “A/D Conversion Characteristics,” corrected P21-11 Section 21.2, “Electrical Characteristics (when VCCE = 3.3V),” added to P21-18 P21-19 Explanation ...
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REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P5-17 Table 5.5.1 corrected P5-19, Description in (2) to (4), Section 5.5.2 changed P5-20 P5-21 Figure 5.5.2 changed P6-43 Note 3 for Section 6.7.1 corrected P6-44 Notes in Figures 6.7.2 and ...
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REVISION HISTORY Rev. Date Page 2.00 Sep 19, 2003 P12-3 Baud rate for UART mode in Table 12.1.1 changed P12-14 Note in Section 12.2.3. (1) corrected P12-24 Last paragraph of Section 12.2.8 changed P12-34 Figure 12.4.1 corrected P12-42 Note deleted ...
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REVISION HISTORY Rev. Date Page Appendix Processing for Input/output ports in Table A3.1.1 alterd 2.00 Sep 19, 2003 3-2, 3-3 Appendix Last item of Appendix 4.8.6 added 4-11 Appendix Last line of the 1st paragraph deleted 4-24 Appendix Description in ...
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How to read internal I/O register tables Bit Numbers: Each register is connected with an internal bus of 16-bit wide, so the bit numbers of the registers located at even addresses are D0-D7, and those at odd addresses are D8-D15. ...
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Table of contents CHAPTER 1 OVERVIEW 1.1 Outline of the 32171 .......................................................................................... 1-2 1.1.1 M32R Family CPU Core .................................................................. 1-2 1.1.2 Built-in Multiply-Accumulate Operation Function ............................. 1-3 1.1.3 Built-in Flash Memory and RAM ...................................................... 1-3 1.1.4 Built-in Clock Frequency Multiplier ...
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CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space ................................................................................ 3-2 3.2 Operation Modes ............................................................................................... 3-6 3.3 Internal ROM Area and External Extension Area ........................................... 3-8 3.3.1 Internal ROM Area ........................................................................... 3-8 3.3.2 External Extension Area ................................................................. 3-8 3.4 Internal ...
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Trap Processing ............................................................................................ 4-20 4.10.1 Trap (TRAP) ................................................................................ 4-20 4.11 EIT Priority Levels ......................................................................................... 4-22 4.12 Example of EIT Processing .......................................................................... 4-23 4.13 Precautions on EIT ....................................................................................... 4-25 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller ...
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Programming of the Internal Flash Memory ................................................. 6-16 6.5.1 Outline of Programming Flash Memory ......................................... 6-16 6.5.2 Controlling Operation Mode during Programming Flash ............... 6-22 6.5.3 Programming Procedure to the Internal Flash Memory ................. 6-25 6.5.4 Flash Program Time ...
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CHAPTER 9 DMAC 9.1 Outline of the DMAC ......................................................................................... 9-2 9.2 DMAC Related Registers .................................................................................. 9-5 9.2.1 DMA Channel Control Register ....................................................... 9-7 9.2.2 DMA Software Request Generation Registers .............................. 9-18 9.2.3 DMA Source Address Registers .................................................... 9-19 9.2.4 DMA ...
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TOP (Output-related 16-bit Timer) ............................................................. 10-46 10.3.1 Outline of TOP ........................................................................... 10-46 10.3.2 Outline of Each Mode of TOP .................................................... 10-48 10.3.3 TOP Related Register Map ........................................................ 10-50 10.3.4 TOP Control Registers ............................................................... 10-53 10.3.5 TOP Counters (TOP0CT-TOP10CT) ......................................... ...
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TML (Input-related 32-bit Timer) .............................................................. 10-132 10.6.1 Outline of TML ......................................................................... 10-132 10.6.2 Outline of TML Operation ........................................................ 10-133 10.6.3 TML Related Register Map ...................................................... 10-134 10.6.4 TML Control Registers ............................................................. 10-135 10.6.5 TML Counters .......................................................................... 10-137 10.6.6 TML ...
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Serial I/O Related Registers ......................................................................... 12-6 12.2.1 SIO Interrupt Related Registers ................................................... 12-7 12.2.2 SIO Interrupt Control Registers ................................................... 12-9 12.2.3 SIO Transmit Control Registers ................................................. 12-13 12.2.4 SIO Transmit/Receive Mode Registers ..................................... 12-15 12.2.5 SIO Transmit Buffer Registers ...
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Typical UART Transmit Operation ............................................. 12-50 12.7 Receive Operation in UART Mode ............................................................. 12-52 12.7.1 Initial Settings for UART Reception ........................................... 12-52 12.7.2 Starting UART Reception .......................................................... 12-54 12.7.3 Processing at End of UART Reception ...................................... 12-54 12.7.4 Typical ...
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Receiving Data Frames .............................................................................. 13-65 13.6.1 Data Frame Receive Procedure ................................................ 13-65 13.6.2 Data Frame Receive Operation ................................................. 13-67 13.6.3 Reading Out Received Data Frames ......................................... 13-69 13.7 Transmitting Remote Frames .................................................................... 13-71 13.7.1 Remote Frame Transmit Procedure .......................................... ...
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CHAPTER 16 WAIT CONTROLLER 16.1 Outline of the Wait Controller ...................................................................... 16-2 16.2 Wait Controller Related Registers ............................................................... 16-4 16.2.1 Wait Cycles Control Register (WTCCR) ...................................... 16-5 16.3 Typical Operation of the Wait Controller .................................................... 16-6 CHAPTER 17 RAM BACKUP ...
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Basic Operation of JTAG ............................................................................. 19-6 19.4.1 Outline of JTAG Operation .......................................................... 19-6 19.4.2 IR Path Sequence ........................................................................ 19-8 19.4.3 DR Path Sequence .................................................................... 19-10 19.4.4 Examining and Setting Data Registers ...................................... 19-12 19.5 Boundary Scan Description Language ..................................................... ...
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CHAPTER 22 TYPICAL CHARACTERISTICS 22.1 A-D Conversion Characteristics .................................................................. 22-2 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1.1 Dimensional Outline Drawing ....................................... Appendix 1-2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 M32R/ECU Instruction Processing Time ..................... Appendix 2-2 APPENDIX 3 PROCESSING OF ...
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Appendix 4.7.4 About the stable operation of DMA transfer ..... Appendix 4-6 Appendix 4.8 Precautions on Multijunction Timers .......................... Appendix 4-7 Appendix 4.8.1 Precautions to be observed when using TOP single-shot output mode .......................... Appendix 4-7 Appendix 4.8.2 Precautions to ...
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Appendix 4.13.3 Processing Analog Input Pin Wiring ............ Appendix 4-28 Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin ............................................. Appendix 4-29 Appendix 4.13.5 Processing Input/Output Ports ..................... Appendix 4-33 (15) ...
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CHAPTER 1 CHAPTER 1 OVERVIEW 1.1 Outline of the 32171 1.2 Block Diagram 1.3 Pin Function 1.4 Pin Layout ...
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Outline of the 32171 1.1.1 M32R Family CPU Core (1) Based on RISC architecture • The 32171 is a 32-bit RISC single-chip microcomputer which is built around the M32R family CPU core (hereafter referred to as the M32R) ...
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Built-in Multiply-Accumulate Operation Function (1) Built-in high-speed multiplier • The M32R incorporates a 32-bit 32-bit 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40 MHz internal CPU clock). (2) Supports Multiply-Accumulate ...
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Built-in Clock Frequency Multiplier • The 32171 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 ...
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Built-in 10-channel DMA • The 10-channel DMA is built-in, supporting data transfers between internal peripheral I/Os or between internal peripheral I/O and internal RAM. Not only can DMA transfer requests be generated in software, but can also be ...
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Eight-level interrupt controller • The interrupt controller manages interrupt requests from each internal peripheral I/O by resolving interrupt priority in eight levels including an interrupt-disabled state. Also, it can accept external interrupt requests due to power-down detection or ...
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Block Diagram Figure 1.2.1 shows a block diagram of the 32171. Features of each block are shown in Tables 1.2.1 through 1.2.3. M32R CPU core (max 40 MHz) Multiplier- accumulator ( Internal flash ...
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Table 1.2.1 Features of the M32R Family CPU Core Functional Block Features M32R family • Bus specifications CPU core Basic bus cycle (when operating with 40 MHz CPU clock) Logical address space: 4Gbytes, linear External extension area: ...
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Table 1.2.3 Features of Internal Peripheral I/O Functional Block Features DMA • 10-channel DMA • Supports transfer between internal peripheral I/Os, between internal RAMs, and between internal peripheral I/O and internal RAM. • Capable of advanced DMA transfer when ...
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... Table 1.2.4 List of Type Name Type Name RAM Size (K bytes) M32171F2VFP 16 M32171F3VFP 16 M32171F4VFP 16 ROM Size (K bytes) Package 256 144LQFP 384 144LQFP 512 144LQFP 1-10 32171 Group User's Manual (Rev.2.00) OVERVIEW 1.2 Block Diagram Number of Pins 144 144 144 ...
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Pin Function Figure 1.3.1 shows pin functions of the M32171FxVFP. Table 1.3.1 explains the pin functions. XIN XOUT VCNT Clock OSC-VCC OSC-VSS Port 7 P70 / BCLK / WR RESET Reset MOD0 Mode MOD1 FP P220 / CTX ...
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Table 1.3.1 Description of the 32171 Pin Function (1/5) Type Pin Name Signal Name Power VCCE Power supply supply VCCI Power supply VDD RAM power supply — FVCC Flash power supply — VSS Ground Clock XIN, Clock XOUT ______ ...
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Table 1.3.1 Description of the 32171 Pin Function (2/5) Type Pin Name Signal Name Data DB0-DB15 Data bus bus ___ Bus CS0, Chip select ___ control CS1 __ RD Read ___ ___ BHW/BHE Byte high write/enable ___ ___ BLW/BLE ...
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Table 1.3.1 Description of the 32171 Pin Function (3/5) Type Pin Name Signal Name A-D AD0IN0 Analog input converter – AD0IN15 VREF0 voltage input ______ Interrupt SBI System break Input controller interrupt Serial I/O SCLKI0 / UART transmit/ Input/output ...
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Table 1.3.1 Description of the 32171 Pin Function (4/5) Type Pin Name Signal Name CAN CTX Data output CRX Data input JTAG JTMS Test mode JTCK clock JTRST Test reset JTDI Serial input JTDO Serial output P00 – P07 ...
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Table 1.3.1 Description of the 32171 Pin Function (5/5) Type Pin Name Signal Name Input/ P124 Input/output output – P127 port 12 port P130 Input/output (Note 1) – P137 port 13 P150, Input/output P153 port 15 P174, Input/output P175 ...
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Pin Layout Figure 1.4.1 shows pin assignments on the M32171FxVFP. Table 1.4.1 lists the pin assignments. JTMS 109 JTCK 110 111 JTRST JTDO 112 JTDI 113 114 P103/TO11 P104/TO12 115 116 P105/TO13 P106/TO14 117 P107/TO15 118 119 P124/TCLK0 ...
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Table 1.4.1 Pin Assignments of the M32171FxVFP No. Pin Name No. 1 P221/CRX 41 2 P225/A12 42 3 OSC-VSS 43 4 XIN 44 5 XOUT 45 6 OSC-VCC 46 7 VCNT 47 8 P30 / A15 48 9 P31 ...
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CHAPTER 2 CHAPTER 2 CPU 2.1 CPU Registers 2.2 General-purpose Registers 2.3 Control Registers 2.4 Accumulator 2.5 Program Counter 2.6 Data Formats 2.7 Precautions on CPU ...
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CPU Registers The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit configuration. 2.2 General-purpose Registers General-purpose registers are 32 ...
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Control Registers There are five control registers-Processor Status Word Register (PSW), Condition Bit Register (CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC). Dedicated "MVTC" and "MVFC" instructions are used to set and read ...
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Processor Status Word Register: PSW (CR0) The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists of a regularly used PSW field and a special BPSW field which is used to ...
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Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the Condition bit (C) from it. The value written to the PSW C bit is reflected in ...
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Accumulator The accumulator (ACC 56-bit register used by DSP function instructions. When read out or written to handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When writing, bits ...
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Data Formats 2.6.1 Data Types There are several data types that can be handled by the M32R's instruction set. These include signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by 2's complements. ...
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Data Formats (1) Data formats in register Data sizes in M32R registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign- extended (LDB, LDH instructions) ...
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Data formats in memory Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can be located at any address. However, halfword data must be located at halfword boundaries (where ...
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Endian The following shows the generally used endian methods and the M32R family endian. Big endian Little endian Note: • Even for bit big endian, H'01 is not B'10000000. Figure 2.6.4 Endian Methods 7700 family MPU name M16C ...
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Transfer instructions • Constant transfer LD24 Rdest, #imm24 LDI Rdest, #imm16 LDI Rdest, #imm8 SETH Rdest, #imm16 • Register to register transfer MV Rdest, Rsrc • Control register transfer MVFC Rdest, CRsrc MVTC Rsrc, CRdest Note: • For ...
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Memory (signed) to register transfer • Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc • Signed 16 bits LD24 Rsrc, #label LDH Rdest, @Rsrc • Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc Figure 2.6.7 Memory ...
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Things to be noted for data transfer Note that in data transfer, data arrangements in registers and those in memory are different. Word data (32 bits) Half-word data (16 bits) Byte data (8 bits) Figure 2.6.9 Difference in ...
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Precautions on CPU • Usage Notes for 0 Division Instruction Problem and Conditions Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction under the conditions described in (1). (1) If ...
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CHAPTER 3 CHAPTER 3 ADDRESS SPACE 3.1 Outline of Address Space 3.2 Operation Modes 3.3 Internal ROM Area and External Extension Area 3.4 Internal RAM Area and SFR Area 3.5 EIT Vector Entry 3.6 ICU Vector Table 3.7 Notes on ...
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Outline of Address Space The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear ad- dress space. The M32R/E's address space consists of the following: (1) User space • Internal ROM area • ...
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M32171F4> Logical address H'0000 0000 2 Gbytes User space H'7FFF FFFF H'8000 0000 Boot 1 Gbyte program space (Note 2) H'BFFF FFFF H'C000 0000 1 Gbyte System space H'FFFF FFFF Note 1: This location varies ...
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M32171F3> Logical address H'0000 0000 2 Gbytes User space H'7FFF FFFF H'8000 0000 Boot 1 Gbyte program space (Note 2) H'BFFF FFFF H'C000 0000 1 Gbyte System space H'FFFF FFFF Note 1: This location varies ...
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M32171F2> Logical address H'0000 0000 2 Gbytes User space H'7FFF FFFF H'8000 0000 Boot 1 Gbyte program space (Note 2) H'BFFF FFFF H'C000 0000 1 Gbyte System space H'FFFF FFFF Note 1: This location varies ...
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Operation Modes The 32171 is placed in one of the following modes by setting its operation mode (using MOD0 and MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section 6.5, ...
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H'0000 0000 Internal ROM (384 Kbytes) H'0005 FFFF H'0006 0000 H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 H'002F FFFF H'0030 0000 H'003F FFFF <Single-chip mode> Figure 3.2.2 M32171F3 Operation Mode and Internal ROM/External extension Areas H'0000 0000 Internal ...
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Internal ROM Area and External Extension Area The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the internal ROM and external extension areas. Of this Mbytes of address space ...
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Internal RAM Area and SFR Area The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of ...
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H’0080 0000 Interrupt controller (ICU) H’0080 007E H’0080 0080 A-D0 converter H’0080 00EE H’0080 0100 Serial I/O0 H’0080 0146 Wait controller H’0080 0180 H’0080 0200 MJT (common part) H’0080 023E H’0080 0240 ...
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Address D0 H’0080 0000 H’0080 0002 H’0080 0004 Interrupt Mask Register (IMASK) SBI Control Register ( SBICR) H’0080 0006 H’0080 0060 CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) H’0080 0062 H’0080 0064 H’0080 0066 SIO2,3 Transmit/Receive Interrupt Control ...
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Address D0 H’0080 00D2 H’0080 00D4 H’0080 00D6 H’0080 00D8 H’0080 00DA H’0080 00DC H’0080 00DE H’0080 00E0 H’0080 00E2 H’0080 00E4 H’0080 00E6 H’0080 00E8 H’0080 00EA H’0080 00EC H’0080 00EE H’0080 0100 SIO23 Interrupt Status Register (SI23STAT) ...
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Address D0 H’0080 0216 H’0080 0218 H’0080 021A H’0080 021C H’0080 021E H’0080 0220 H’0080 0222 H’0080 0224 H’0080 0226 H’0080 0228 H’0080 022A H’0080 0230 TOP Interrupt Control Register 0 (TOPIR0) H’0080 0232 TOP Interrupt Control Register 2 ...
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Address D0 H'0080 0296 H'0080 0298 H'0080 029A H'0080 029C H'0080 029E H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6 H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 ...
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Address D0 H'0080 031C H'0080 0320 H'0080 0322 H'0080 0324 H'0080 0326 H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336 H'0080 0340 H'0080 0342 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A TIO4 Control Register (TIO4CR) H'0080 0350 H'0080 ...
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Address D0 H'0080 03BC H'0080 03BE H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA TMS0 Control Register (TMS0CR) H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8 H'0080 03E0 H'0080 03E2 H'0080 03EA H'0080 ...
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Address D0 H’0080 0430 DMA2 Channel Control Register (DM2CNT) H’0080 0432 H’0080 0434 H’0080 0436 H’0080 0438 DMA7 Channel Control Register (DM7CNT) H’0080 043A H’0080 043C H’0080 043E H’0080 0440 DMA3 Channel Control Register (DM3CNT) H’0080 0442 H’0080 0444 ...
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Addres s D0 H’0080 0716 P22 Data Register (P22DATA) H’0080 0720 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) H’0080 0722 P4 Direction Register (P4DIR) H’0080 0724 P6 Direction Register (P6DIR) H’0080 0726 P8 Direction Register (P8DIR) H’0080 0728 ...
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Address D0 H’0080 0FF4 H’0080 0FF6 H’0080 0FF8 H’0080 0FFA H’0080 0FFC H’0080 0FFE H’0080 1000 H’0080 1002 H’0080 1004 H’0080 1006 H’0080 1008 H’0080 100A CAN0 Receive Error Count Register (CAN0REC) H’0080 100C H’0080 100E H’0080 1010 H’0080 ...
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Address D0 H'0080 1100 CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0) H'0080 1102 CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0) H'0080 1104 CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2) H'0080 1106 CAN0 Message Slot 0 Data 0 (C0MSL0DT0) H'0080 ...
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Addres s D0 H'0080 1154 CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2) H'0080 1156 CAN0 Message Slot 5 Data 0 (C0MSL5DT0) H'0080 1158 CAN0 Message Slot 5 Data 2 (C0MSL5DT2) H'0080 115A CAN0 Message Slot 5 Data 4 (C0MSL5DT4) ...
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Addres s D0 H'0080 11A8 CAN0 Message Slot 10 Data 2 (C0MSL10DT2) H'0080 11AA CAN0 Message Slot 10 Data 4 (C0MSL10DT4) H'0080 11AC CAN0 Message Slot 10 Data 6 (C0MSL10DT6) H'0080 11AE H'0080 11B0 CAN0 Message Slot 11 Standard ...
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EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM/external extension areas. Instructions for branching to the start addresses of respective EIT event handlers are written here. Note that it is branch ...
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ICU Vector Table The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set at the ad- dresses shown below. For ...
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Address D0 H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 ...
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Notes on Address Space • Virtual flash emulation function The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can ...
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CHAPTER 4 CHAPTER 4 4.1 Outline of EIT 4.2 EIT Events 4.3 EIT Processing Procedure 4.4 EIT Processing Mechanism 4.5 Acceptance of EIT Events 4.6 Saving and Restoring the PC and PSW 4.7 EIT Vector Entry 4.8 Exception Processing 4.9 ...
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Outline of EIT If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred ...
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EIT Events 4.2.1 Exception (1) Reserved Instruction Exception (RIE) Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) is generated when an attempt is ...
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EIT Processing Procedure EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except ...
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When an EIT is accepted, the M32R/ECU saves the PC and PSW (as will be described later) and branches to the EIT vector. The EIT vector has an entry address assigned for each EIT. This is where the BRA ...
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EIT Processing Mechanism The M32R/ECU's EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC register and the BPSW ...
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Acceptance of EIT Events When an EIT event occurs, the M32R/ECU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing ...
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Saving and Restoring the PC and PSW The following describes operation of the M32R at the time when it accepts an EIT and when it executes the "RTE" instruction. (1) Hardware preprocessing when an EIT is accepted (a) ...
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Save SM, IE, and C bits (b) Update SM, IE, and C bits (e) Restore BSM, BIE, and BC bits from backup bits The values of BSM, BIE, and BC bits after execution of the "RTE" instruction are ...
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EIT Vector Entry The EIT vector entry is located in the user space starting from address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry Name Abbreviation Vector Address Reset Interrupt RI ...
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Exception Processing 4.8.1 Reserved Instruction Exception (RIE) [Occurrence Conditions] Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a ...
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Address H'00 Return H'04 RIE occurred address H'08 H'0C ~ Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0020 in ...
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Address Exception (AE) [Occurrence Conditions] Address Exception (AE) is generated when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause ...
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Address H'00 Return H'04 AE occurred address H'08 H'0C ~ Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry Control branches to the address H'0000 0030 in the ...
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Interrupt Processing 4.9.1 Reset Interrupt (RI) [Occurrence Conditions] Reset Interrupt (RI) is unconditionally accepted in any machine cycle by pulling the RESET input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] ...
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System Break Interrupt (SBI) System Break Interrupt (SBI emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked ...
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Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits-the BSM, BIE, and BC bits. BSM BIE BC (2) Updating SM, IE, and C ...
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External Interrupt (EI) An external interrupt is generated upon an interrupt request which is output by the 32171's internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, refer ...
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Processing] (1) Saving SM, IE, and C bits The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE, and BC bits. BSM BIE BC (2) Updating SM, IE, ...
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Trap Processing 4.10.1 Trap (TRAP) [Occurrence Conditions] Traps refer to software interrupts which are generated by executing the "TRAP" instruction. Sixteen distinct traps are generated, each corresponding to one of "TRAP" instruction operands 0-15. Accordingly, sixteen vector entries ...
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Address H'00 H'04 TRAP occurred Return H'08 address H'0C ~ BPC Figure 4.10.1 Example of a Return Address for Trap (TRAP) (4) Branching to the EIT vector entry Control branches to the addresses H'0000 0040 through H'0000 ...
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EIT Priority Levels The table below lists the priority levels of EIT events. When multiple EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT ...
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Example of EIT Processing (1) When RIE, AE, SBI, EI, or TRAP occurs singly RIE, AE, SBI, EI, or TRAP occurrs Singly Return address A: Figure 4.12.1 Processing of Events When RIE, AE, SBI, EI, or TRAP Occurs ...
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EIT vector entry ~ BRA instruction ~ PC BPC Hardware PSW (B)PSW preprocessing Program being executed • • • • EIT • event • • occurs • • • • • • • (B)PSW Hardware BPC PC postprocessing Figure ...
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Precautions on EIT Address Exception requires caution because when an address exception occurs pursuant to execution of an instruction (one of the following three) that uses the “register indirect + register update” addressing mode, the value of the ...
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This is a blank page. * 4-26 32171 Group User's Manual (Rev.2.00) EIT 4.13 Precautions on EIT ...
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CHAPTER 5 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller (ICU) 5.2 ICU Related Registers 5.3 Interrupt Request Sources in Internal Peripheral I/O 5.4 ICU Vector Table 5.5 Description of Interrupt Operation 5.6 Description of System Break ...
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Outline of the Interrupt Controller (ICU) The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are notified to the M32R CPU as external ...
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SBI Peripheral circuits Interrupt Edge- recognized request Edge- Interrupt recognized request Edge- Interrupt recognized request . . . . . . . . . . . . . . Level- Interrupt recognized control circuit Level- Interrupt recognized control circuit ...
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ICU Related Registers The diagram below shows a register map associated with the Interrupt Controller (ICU). Address D0 H'0080 0000 H'0080 0002 Interrupt Request Mask Register (IMASK) H'0080 0004 SBI Control Register (SBICR) H'0080 0006 ~ ~ CAN0 ...
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Interrupt Vector Register Interrupt Vector Register (IVECT Bit Name 0 – 15 IVECT (16 low-order bits of ICU vector table address) Note: • This register must always be accessed in halfwords. (This is ...
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Interrupt Request Mask Register Interrupt Request Mask Register (IMASK Bit Name 0 – functions assigned 5– 7 IMASK (Interrupt request mask bit) The Interrupt Request Mask Register (IMASK) is used to finally determine ...
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SBI (System Break Interrupt) Control Register SBI (System Break Interrupt) Control Register Bit Name 0 – functions assigned 7 SBI REQ (SBI request bit SBI is not requested Note 1: This ...
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Interrupt Control Registers CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) A-D0 Converter Interrupt Control Register (IAD0CCR) SIO0 Transmit Interrupt Control Register ...
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Bit Name 0 – functions assigned (8-10) 3 IREQ (11) Interrupt request bit 4 No functions assigned (12) 5-7 ILEVEL (13-15) Interrupt priority level bits (1) IREQ (Interrupt Request) bit (D3 ...
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Interrupt request from each internal peripheral I Data bus Set/clear d5-7 or d13-15 Figure 5.2.2 Configuration of the Interrupt Control Register (Edge-recognized Type) Interrupt request from each group internal peripheral I/O Data bus ...
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ILEVEL (Interrupt Priority Level) (D5-D7 or D13-D15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set priority level 7 to disable interrupts from some internal peripheral I/O or priority levels 0-6 to ...
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Interrupt Request Sources in Internal Peripheral I/O The interrupt controller receives as its inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD, and CAN. For details about these interrupts, refer to each section ...
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ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 22-source interrupts are assigned the following addresses: Table 5.4.1 ICU Vector Table Addresses Interrupt Source ...
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Address D0 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 ...
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Address H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC ...
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Description of Interrupt Operation 5.5.1 Acceptance of Internal Peripheral I/O Interrupts An interrupt from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register ...
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Table 5.5.1 Hardware-fixed Priority Levels Priority Interrupt Request Source High MJT Input Interrupt Request 4 (TIN3 input) MJT Input Interrupt Request 3 (TIN20-TIN23 input) MJT Input Interrupt Request 2 (TIN16-TIN19 input) MJT Input Interrupt Request 1 (TIN0 input) MJT ...
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Table 5.5.2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set 0 (ILEVEL="000") 1 (ILEVEL="001") 2 (ILEVEL="010") 3 (ILEVEL="011") 4 (ILEVEL="100") 5 (ILEVEL="101") 6 (ILEVEL="110") 7 (ILEVEL="111") INTERRUPT CONTROLLER (ICU) 5.5 Description of Interrupt Operation IMASK values at which ...
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Processing of Internal Peripheral I/O Interrupts by Handler (1) Branching to the interrupt handler When the CPU accepts an interrupt, control branches to the EIT vector entry after hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." ...
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Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. ...
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EI (External Interrupt) vector entry H'0000 0080 BRA instruction Hardware preprocessing when EIT is accepted (Note 1) Program being executed Interrupt generated Hardware postprocessing when RTE instruction is executed (Note 1) Note 1: For operations at EIT acceptance and ...
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Description of System Break Interrupt (SBI) Operation 5.6.1 Acceptance of SBI System Break Interrupt (SBI emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer. ...
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CHAPTER 6 CHAPTER 6 INTERNAL MEMORY 6.1 Outline of the Internal Memory 6.2 Internal RAM 6.3 Internal Flash Memory 6.4 Registers Associated with the Internal Flash Memory 6.5 Programming of the Internal Flash Memory 6.6 Boot ROM 6.7 Virtual Flash ...
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Outline of the Internal Memory The 32171 internally contains the following types of memory: • 16 Kbyte RAM • 512 Kbyte, 384 Kbyte, or 256 Kbyte flash memory 6.2 Internal RAM Specifications of the 32171's internal RAM are ...
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Internal Flash Memory Specifications of the 32171's internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory Item Specification Capacity M32171F4 : 512 Kbytes Location address M32171F4 : H'0000 0000 - H'0007 FFFF M32171F3 ...
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Flash Mode Register Flash Mode Register (FMOD Bit Name functions assigned 7 FPMOD (External FP pin status) The Flash Mode Register (FMOD read-only status register, with its FPMOD bit ...
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Flash Status Registers The 32171 has two registers to indicate the flash memory status, one of which is Flash Status Register 1 (FSTAT1) located in the SFR area (address: H'0080 07E1), and the other is Flash Status Register ...
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Flash Status Register 2 (FSTAT2 FBUSY D Bit Name 8 FBUSY (Flash busy functions assigned 10 ERASE (Auto Erase operating condition) 11 WRERR1 (Program operating condition) 12 WRERR2 (Program operating condition ...
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WRERR2 (Program operating condition) bit (D12) The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error. When WRERR2 = 0, it means the program operation terminated normally; when WRERR2 ...
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Flash Control Registers Flash Control Register 1 (FCNT1 Bit Name functions assigned 3 FENTRY (Flash mode entry functions assigned 7 FEMMOD (Virtual flash emulation mode) The Flash ...
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When using a program in the flash memory while the FENTRY bit = 0, the EI vector entry is located at address H'0000 0080 of the flash memory. When running a flash write/erase program in RAM while the FENTRY ...
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Flash Control Register 2 (FCNT2 Bit Name functions assigned 15 FPROT (Unlock) The Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (to disable ...
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Flash Control Register 3 (FCNT3 Bit Name functions assigned 7 FELEVEL (Raise erase margin) The Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory ...
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Flash Control Register 4 (FCNT4 Bit Name functions assigned 15 FRESET (Reset flash) The Flash Control Register 4 (FCNT4) controls canceling program/erase operation in the middle and initializing each status bit of ...
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Figure 6.4.3 FCNT4 Register Usage Example 1 (Initializing Flash Status Register 2) Flash programming or erasing timed out Figure 6.4.4 FCNT4 Register Usage Example 2 (Forcibly terminating flash memory programming/erasing) 6.4 Registers Associated with the Internal Flash Memory FENTRY=0 ...
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Virtual Flash L Bank Register Virtual Flash L Bank Register 0 (FELBANK0) MOD ENL Bit Name 0 MODENL (Virtual flash emulation enable functions assigned LBANKAD (L ...
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Virtual Flash S Bank Registers Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) MOD ENS Bit Name 0 MODENS (Virtual flash emulation enable ...
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Programming of the Internal Flash Memory 6.5.1 Outline of Programming Flash Memory When programming to the internal flash memory, there are following two methods to use depending on situation: (1) When the write program does not exist in ...
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Flash E/W enable mode (FENTRY=1) H'0000 0000 Internal ROM area H'0080 3FFF H'0080 4000 Internal RAM H'00FF FFFF Figure 6.5.1 EI Vector Entry When in Flash E/W Enable Mode 6.5 Programming of the Internal Flash Memory Normal mode H'0000 ...
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When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to program to the flash memory. To transfer the write data, use serial I/O1 in ...
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Mode selected POWER ON RESET MOD0 MOD1 FP FENTRY Figure 6.5.3 Internal Flash Memory Write Timings (when the write program does not exist in the flash memory) 6.5 Programming of the Internal Flash Memory Reset singal deasserted (Boot program ...
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When the write program already exists in the internal flash memory Use the flash write/erase program already stored in the internal flash memory to program to the flash memory. For program to the flash memory, use the internal ...
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RESET "L" MOD0 MOD1 "H" or "L" (Single-chip or external extension) "H" or "L" FP FENTRY Flash write/erase program Figure 6.5.5 Internal Flash Memory Write Timings (when the write program already exists in the flash memory) ...
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Controlling Operation Mode during Programming Flash The device's operation modes are set by MOD0, MOD1, and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be set during flash program. Table 6.5.1 ...
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Entering flash E/W enable mode Flash E/W enable mode can be entered only when the device is operating in single-chip mode or external extension mode. Namely, you can enter flash E/W enable mode only when the FP pin ...
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Enter one of the following modes: • Single-chip mode + flash E/W enable mode • Boot mode + flash E/W enable mode • External extension mode + flash E/W enable mode Transfer E/W program to internal RAM in each ...
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Programming Procedure to the Internal Flash Memory To program to the internal flash memory, set the device's operation mode to enter flash E/W enable mode first and then use the flash write/erase program that has already been transferred ...
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Read Array command Read mode is entered by writing command data H'FFFF to any address of the internal flash memory. Then read the flash memory address you want to read out, and the content of that address will ...
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Table 6.5.3 M32171F4 Target Blocks and Specified Addresses Target Block Table 6.5.4 M32171F3 Target Blocks and Specified Addresses Target Block ...
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M32171F4's Internal Flash Memory Area (512KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 H'0001 FFFF H'0002 0000 H'0002 FFFF H'0003 0000 H'0003 FFFF H'0004 0000 H'0004 FFFF H'0005 ...
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M32171F3’s Internal Flash Memory Area (384KB) H’0000 0000 H’0000 3FFF H’0000 4000 H’0000 5FFF H’0000 6000 H’0000 7FFF H’0000 8000 H’0000 FFFF H’0001 0000 H’0001 FFFF H’0002 0000 H’0002 FFFF H’0003 0000 H’0003 FFFF H’0004 0000 H’0004 FFFF H’0005 ...
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M32171F2's Internal Flash Memory Area (256KB) H'0000 0000 H'0000 3FFF H'0000 4000 H'0000 5FFF H'0000 6000 H'0000 7FFF H'0000 8000 H'0000 FFFF H'0001 0000 H'0001 FFFF H'0002 0000 H'0002 FFFF H'0003 0000 H'0003 FFFF Figure 6.5.9 Block Configuration of ...
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Block Erase command The Block Erase command erases the contents of internal flash memory one block at a time. For Block Erase, write the command data H'2020 to any address of the internal flash memory. Next, write the ...
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Read Lock Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program/erase. Write the command data H'7171 to any address of the internal flash memory. ...
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Follow the procedure described below to write to the lock bits. a) Setting the lock bit to 0 (protect the block) Issue the Lock Bit Program command (H'7777) to the memory block you want to protect. b) Setting the ...
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Increment the previous write address by 2 and write the next data to the new address. Read any address of internal flash memory Go to next page Note 1: Start ...
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Write Lock Bit Program command (H'7777) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to protect. Written to the lock bit by program (by hardware timer ...
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Write Erase command (H'2020) to any address of internal flash memory. Write Verify command (H'D0D0) to the last even address of the block you want to erase. Flash memory contents erased by (by hardware timer or software timer) Read ...
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Write Erase All Unlock Block command (H'A7A7) to any address of internal flash Write Verify command (H'D0D0) to any address in memory blocks you want to Flash memory contents erased by Erase program (Note 1) (by hardware timer or ...
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Figure 6.5.15 Read Status Register Figure 6.5.16 Clear Status Register Figure 6.5.17 Read Lock Bit Status Register 6.5 Programming of the Internal Flash Memory START Write Read Status command (H'7070) to any address of internal flash memory. Read any ...
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Flash Program Time (for Reference) The time required for programming to the internal flash memory is shown below for your reference. (1) M32171F4 a) Transfer time by SIO (for a transfer data size of 512 KB) 1/57600 bps ...
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M32171F2 a) Transfer time by SIO (for a transfer data size of 256 KB) 1/57600 bps ¥ 1 (frame) ¥ 11 (number of transfer bits) ¥ 256 KB b) Flash program time 256 KB/256-byte block ¥ ...
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Boot ROM The table below shows boot memory specifications of the 32171. Table 6.6.1 Boot Memory Specifications Item Specification Capacity 8 Kbytes Location address H'8000 0000 - H'8000 1FFF Wait insertion Operates with no wait states (with 40 ...
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Virtual-Flash Emulation Function The 32171 can map one 8-Kbyte block of internal RAM beginning with the start address into one of 8-Kbyte areas (L banks) of the internal flash memory and can map up to two 4-Kbyte blocks ...
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Virtual-Flash Emulation Areas The following shows the areas effective for the virtual-flash emulation function. Select one of 8-Kbyte blocks or L banks of flash memory using the Virtual-Flash L Bank Register (FELBANK0) (by setting the seven address bits ...
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H'0000 0000 H'0000 2000 H'0000 4000 H'0007 C000 H'0007 E000 Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area to ...
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H'0000 0000 L bank 0 (8Kbytes) H'0000 2000 L bank 1 (8Kbytes) H'0000 4000 L bank 2 (8Kbytes) H'0005 C000 L bank 46 (8Kbytes) H'0005 E000 L bank 47 (8Kbytes) Notes: • If the Virtual-Flash Emulation Enable ...
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H'0000 0000 H'0000 2000 H'0000 4000 H'0003 C000 H'0003 E000 Notes: • If the Virtual-Flash Emulation Enable bit is enabled while the same bank area is set in multiple Virtual-Flash Bank Registers, the internal RAM area (8 ...
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L bank L bank 0 L bank 1 L bank 2 L bank 62 L bank 63 Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 ...
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L bank L bank 0 L bank 1 L bank 2 L bank 46 L bank 47 Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 ...
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L bank L bank 0 L bank 1 L bank 2 L bank 30 L bank 31 Note 1: Set the seven bits A12-A18 of the start address (32-bit) of each L bank of flash memory divided every 8 ...
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Entering Virtual Flash Emulation Mode To enter Virtual Flash Emulation Mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit to 1. After entering Virtual Flash Emulation Mode, set the Virtual Flash Bank Register MODEN bit to 1 ...
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Application Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function, you can rewrite data in the flash memory successively. (1) Operation when reset Bank ...
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Program operation using RAM block 1 Flash Bank xx Initial value RAM block 0 RAM block 1 (5) Program operation changed from RAM block 1 to RAM block 0 Bank xx Initial value RAM block 0 RAM block ...
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Connecting to A Serial Programmer When you reprogram the internal flash memory using a general-purpose serial programmer in Boot Flash E/W Enable mode, you need to process the pins on the 32171 shown below to make them suitable ...
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The diagram below shows an example of user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer programs to the flash memory in clock-synchronized serial mode. No communication problems ...
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Internal Flash Memory Protect Functions The 32171’s internal flash memory has the following four protect functions to prevent unintended reprogramming by an erratic operation or unauthorized copying or reprogramming of its contents. (1) Flash memory protect ID When ...
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Precautions to Be Taken When Reprogramming Flash Memory 6.10 Precautions to Be Taken When Reprogramming Flash Memory The following describes precautions to be taken when you reprogram the flash memory using a general-purpose serial programmer in Boot Flash ...
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CHAPTER 7 CHAPTER 7 RESET 7.1 Outline of Reset 7.2 Reset Operation 7.3 Internal State after Exiting Reset 7.4 Things To Be Considered after Exiting Reset ...
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Outline of Reset The device is reset by applying a low-level signal to the RESET input pin. The device is gotten out of a reset state by releasing the RESET input back high, upon which the reset vector ...
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Internal State after Exiting Reset The table below lists the register state of the device after it has gotten out of reset. For details about the initial register state of each internal peripheral I/O, refer to each section ...
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The pins that were set for input when reset high-impedance state (Hi-Z). Here, “when reset” means that the RESET# pin input is held low (the device being reset) and is released back high (the device being ...
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Table 7.3.3 Pin Status When Reset (2/4) Function Pin NO. Pin Name Other than Port 27 P01/DB1 P01 28 P02/DB2 P02 29 P03/DB3 P03 30 P04/DB4 P04 31 P05/DB5 P05 32 P06/DB6 P06 33 P07/DB7 P07 34 P10/DB8 P10 ...
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Table 7.3.4 Pin Status When Reset (3/4) Function Pin NO. Pin Name Other than Port 62 VSS - 63 P174 TXD2 P174/TXD2 64 P175 RXD2 P175/RXD2 65 - VCCE VCCE 66 P82 TXD0 P82/TXD0 67 P83 RXD0 P83/RXD0 68 ...
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Table 7.3.5 Pin Status When Reset (4/4) Function Pin NO. Pin Name Other than Port 121 P126/TCLK2 P126 TCLK2 122 P127/TCLK3 P127 TCLK3 123 VCCI - 124 P130/TIN16 P130 TIN16 125 P131/TIN17 P131 TIN17 126 P132/TIN18 P132 TIN18 127 ...
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Things To Be Considered after Exiting Reset • Input/output ports After exiting reset, the 32171's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, ...
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CHAPTER 8 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports 8.2 Selecting Pin Functions 8.3 Input/Output Port Related Registers 8.4 Port Peripheral Circuits 8.5 Precautions on Input/output Ports ...
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Outline of Input/Output Ports The 32171 has a total of 97 input/output ports consisting of P0–P13, P15, P17, and P22 (with P5 reserved for future use, however). These input/output ports can be used as input ports or output ...
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Table 8.1.1 Outline of Input/Output Ports Item Specification Number of ports Total 97 lines P10 : P11 : P12 : P13 : P15 : P17 : P22 : Port function ...
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Selecting Pin Functions Each input/output port serves dual purposes along with other internal peripheral I/Os or external extension bus signal lines (or triple purposes along with multiple functions of peripheral I/O). Pin functions are selected according to the ...