HD74AC373FPEL Renesas Electronics Corporation., HD74AC373FPEL Datasheet

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HD74AC373FPEL

Manufacturer Part Number
HD74AC373FPEL
Description
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD74AC373FPEL
Manufacturer:
RENESAS
Quantity:
20 000
HD74AC373P
HD74AC373FPEL
HD74AC373RPEL
HD74AC373TELL
HD74AC373/HD74ACT373
Octal Transparent Latch with 3-State Output
Description
The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications.
The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the
setup time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High, the bus output
is in the high impedance state.
Features
Notes: 1. Please consult the sales office for the above package availability.
Rev.2.00, Jul.16.2004, page 1 of 9
Eight Latches in a Single Package
3-State Outputs for Bus Interfacing
Outputs Source/Sink 24 mA
HD74AC373 has TTL-Compatible Inputs
Ordering Information: Ex. HD74AC373
Part Name
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
DIP-20 pin
SOP-20 pin (JEITA)
SOP-20 pin (JEDEC) FP-20DBV
TSSOP-20 pin
Package Type
DP-20N, -20NEV P
FP-20DAV
TTP-20DAV
Package Code Package Abbreviation Taping Abbreviation (Quantity)
RP
T
FP
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
(Previous ADE-205-394 (Z))
REJ03D0273–0200Z
Jul.16.2004
Rev.2.00

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HD74AC373FPEL Summary of contents

Page 1

... Outputs Source/Sink 24 mA HD74AC373 has TTL-Compatible Inputs Ordering Information: Ex. HD74AC373 Part Name Package Type HD74AC373P DIP-20 pin HD74AC373FPEL SOP-20 pin (JEITA) HD74AC373RPEL SOP-20 pin (JEDEC) FP-20DBV HD74AC373TELL TSSOP-20 pin Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code ...

Page 2

HD74AC373/HD74ACT373 Pin Arrangement Logic Symbol Pin Names D – D Data Inputs Latch Enable Input OE Output Enable Input O – O 3-State Latch Outputs 0 7 Rev.2.00, Jul.16.2004, page ...

Page 3

HD74AC373/HD74ACT373 Truth Table Inputs High Voltage Level L : Low Voltage Level Z : High Impedance X : Immaterial O : Previous O before Low-to-High Transition ...

Page 4

HD74AC373/HD74ACT373 Recommended Operating Conditions: HD74AC373 Item Supply voltage Input and Output voltage Operating temperature Input rise and fall time (except Schmitt inputs) V 30 Characteristics: HD74AC373 Item Sym- Vcc bol (V) Input Voltage V ...

Page 5

HD74AC373/HD74ACT373 DC Characteristics: HD74ACT373 Item Sym bol (V) Input voltage V 4.5 IH 5.5 V 4.5 IL 5.5 Output voltage V 4.5 OH 5.5 4.5 5.5 V 4.5 OL 5.5 4.5 5.5 Input current I 5 ...

Page 6

HD74AC373/HD74ACT373 AC Characteristics: HD74AC373 Item Symbol Propagation delay t PLH Propagation delay t PHL Propagation delay t PLH Propagation delay t PHL ...

Page 7

HD74AC373/HD74ACT373 Package Dimensions 20 1 0.89 1.27 Max 2.54 ± 0. 0.89 1.27 Max 2.54 ± 0.25 *NI/Pd/AU Plating Rev.2.00, Jul.16.2004, page 24.50 25.40 Max 11 10 1.30 0.48 ± 0.10 Package Code JEDEC JEITA ...

Page 8

HD74AC373/HD74ACT373 13 Max 20 1 0.80 Max 1.27 *0.40 ± 0.06 *Ni/Pd/Au plating 12.8 13.2 Max 20 1 0.935 Max 1.27 *0.40 ± 0.06 *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 12 0.70 ± 0.20 0.15 0.12 ...

Page 9

HD74AC373/HD74ACT373 6.50 6.80 Max 20 1 *0.20 ± 0.05 0.65 Max *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 0.65 0.13 M 6.40 ± 0.20 0.10 Package Code JEDEC JEITA Mass (reference value January, 2003 Unit: ...

Page 10

Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

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