BU8710AKS Rohm, BU8710AKS Datasheet
BU8710AKS
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BU8710AKS Summary of contents
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... Communication ICs 4-channel ADPCM transcoder for digital cordless telephone base stations BU8710AKS This is an ADPCM transcoder which conforms to the G.721 standards listed in the 1988 edition of the CCITT recommen- dations. Simultaneous processing of four encoder and decoder channels is possible, enabling superb affinity with the quadruple TDMA which is a standard for PHS (personal handy phone) systems ...
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... Communication ICs FBlock diagram 100 BU8710AKS ...
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... Communication ICs FAbsolute maximum ratings (Ta = 25_C) FRecommended operating conditions (Ta = 25_C) FPin descriptions BU8710AKS 101 ...
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... Communication ICs 102 BU8710AKS ...
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... Communication ICs FElectrical characteristics DC characteristics (unless otherwise noted 25_C 5.0V) DD BU8710AKS 103 ...
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... Communication ICs AC characteristics (unless otherwise noted 25_C, V 104 = 5.0V) DD BU8710AKS ...
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... Communication ICs FInput / output signal timing charts BU8710AKS 105 ...
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... Communication ICs 106 BU8710AKS ...
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... Communication ICs BU8710AKS 107 ...
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... Note: In Figures when the 64kbps data through mode is set, the normal 4-bit output encoder output is equivalent to the timing of the decoder 8-bit output (corresponding to Figure 5), and the normal 4-bit input decoder input is equivalent to the timing of the encoder 8-bit input (corresponding to Figure 2). Correspondence between encoder and decoder input pins Correspondence between encoder and decoder output pins 108 BU8710AKS ...
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... Communication ICs FControl signal timing charts BU8710AKS 109 ...
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... Communication ICs 110 BU8710AKS ...
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... When using the 4-bit interface, use MDAT3 the lower bit side. S MRDRQ Sends a request to the CPU to read data channels where silence detection is en- abled silence state is detected, MRDRQ goes LOW. BU8710AKS 111 ...
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... Communication ICs 1) CPU interface truth table 112 BU8710AKS ...
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... Communication ICs BU8710AKS 113 ...
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... Channel 1-A encoder initialized G G 114 RESE1B Channel 1-B encoder initialized G G RESE2A Channel 2-A encoder initialized G G RESE2B Channel 2-B encoder initialized G G RESD1A Channel 1-A decoder initialized G G RESD1B Channel 1-B decoder initialized G G RESD2A Channel 2-A decoder initialized G G RESD2B Channel 2-B decoder initialized G G BU8710AKS ...
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... VDFxxx, one or more bits are HIGH), the MRDRQ pin goes LOW. If silence detection is not in effect on any of the encoders on channels for which it is enabled (all bits of register VDFxxx are LOW), the MRDRQ pin is HIGH. BU8710AKS 115 ...
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... THRD1A 64 kbps data through mode for Channel 1-A decoder THRD1B 64 kbps data through mode for Channel 1-B decoder THRD2A 64 kbps data through mode for Channel 2-A decoder THRD2B 64 kbps data through mode for Channel 2-B decoder BU8710AKS ...
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... This is the serial interface which is used to input and out- put data to and from the 4-channel encoders and decod- ers. It accommodates all interfaces : the long frame in normal mode, the short frame in normal mode, and the synchronous mode. Interfaces and signal names BU8710AKS 117 ...
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... Enable sig- nal. S Synchronous mode This is a special timing mode. In this mode, data is input and output in sequential order, immediately following the rising edge of the Enable signal, regardless of the pulse width of the Enable signal. 118 BU8710AKS ...
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... Communication ICs 1) Timings for the various modes Figures show the relations between the serial clock, Enable signal, and data for the various encoder and decoder input and output, in the normal mode and the synchronous mode. BU8710AKS 119 ...
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... Communication ICs 120 BU8710AKS ...
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... ( ( ( (k) BU8710AKS is updated the data through and 4 is updated remains the same. is latched 6 . With Serial input data targeted for calculation Parallel input data targeted for calculation ...
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... As shown in Figure 21, if the input clock exceeds 64kHz and the output clock exceeds 32kHz, and the Input En- able and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 21. 122 BU8710AKS ...
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... As shown in Figure 22, if the input clock exceeds 32kHz and the output clock exceeds 64kHz, and the Input En- able and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 22. BU8710AKS 123 ...
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... As shown in Figure 23, if the input / output clock exceeds 64 kHz and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will oc- cur. Delays occurring under other conditions can also be determined based on Figure 23. 124 BU8710AKS ...
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... As shown in Figure 24, if the input / output clock exceeds 32kHz and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will oc- cur. Delays occurring under other conditions can also be determined based on Figure 24. BU8710AKS 125 ...
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... VDLV12 to 00). The reference level is applied as an absolute value will be within a range of VDLV to – VDLV. Condition 3 Conditions 1 and 2 must be met contin- uously for more than a given period of time (set using registers VDTIM5 to 0). Figure 25 shows silence detection conditions. 126 BU8710AKS ...
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... Communication ICs FApplication BU8710AKS 127 ...
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... Communication ICs FBoard component layout Connector pin correspondence table 128 BU8710AKS ...
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... Communication ICs Items relating to switches and LEDs BU8710AKS 129 ...
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... Turn on SW14 to read the data for the command num- 2 ber set using SW1 X SW4 in serial time. The results are displayed by LED1 X LED8. If the settings for SW1 X SW4 have been changed, the results displayed will change accordingly. Data can also be written while other data is being read. BU8710AKS ...