LAN91C96 Standard Microsystems, LAN91C96 Datasheet
LAN91C96
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LAN91C96 Summary of contents
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... Buses with No Wait States Flexible Bus Interface 16 Bit Data and Control Paths Fast Access Time 1 Refer to Description of Pin Functions on Page 16 for 5V tolerant pins SMSC LAN91C965v&3v LAN91C96 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Pipelined Data Path Handles Block Word Transfers for any Alignment High Performance Chained (" ...
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... LAN91C96 TQFP for 100 Pin TQFP Package LAN91C96-MS for 100 pin Lead Free QFP Package LAN91C96-MU for 100 pin Lead Free TQFP Package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. ...
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... Functional Description _____________________________________________________________________ 22 5.1 Buffer Memory _______________________________________________________________________________ 23 5.2 Interrupt Structure____________________________________________________________________________ 30 5.3 Reset Logic___________________________________________________________________________________ 31 5.4 Power Down Logic States_______________________________________________________________________ 31 5.5 LAN91C96 Power Down States __________________________________________________________________ 32 5.6 PCMCIA CONFIGURATION REGISTERS DESCRIPTION ________________________________________ 35 Chapter 6 Frame Format in Buffer Memory for Ethernet __________________________________________________ 37 Chapter 7 Registers Map in I/O Space __________________________________________________________________ 41 7.1 I/O Space Access ______________________________________________________________________________ 41 7.2 I/O Space Registers Description _________________________________________________________________ 41 ...
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... Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................24 Figure 5.2 – Transmit Queues and Mapping................................................................................................................25 Figure 5.3 – Receive Queues and Mapping.................................................................................................................26 Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path...................................................................................27 Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................28 Figure 6.1 – Data Frame Format..................................................................................................................................37 Figure 6.2 - LAN91C96 Registers ................................................................................................................................40 Figure 7.1 – ...
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... Figure 12.26 – Input Clock Timing .............................................................................................................................122 Figure 12.27 – Memory Write Timing .........................................................................................................................122 Figure 12.28 - 100 PIN QFP Package........................................................................................................................123 Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124 Table 5.1 - LAN91C96 Address Space ........................................................................................................................29 Table 5.2 - Bus Transactions In LOCAL BUS Mode ....................................................................................................29 Table 5.3 - Bus Transactions In PCMCIA Mode...........................................................................................................30 Table 5.4 - Bus Transactions In 68000 Mode................................................................................................................30 Table 5 ...
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... CPU and bus platforms due to its flexible bus interface, flat memory structure (no pointers), and its loosely coupled buffered architecture (not sensitive to latency). The LAN91C96 is available in 100-pin QFP and TQFP (1.0 mm body thickness) packages. The low profile TQFP is ideal for mobile applications such as PC Card LAN adapters. The LAN91C96 operates with a single power supply voltage of 5 ...
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... AUI interface. For twisted pair networks, LAN91C96 integrates the twisted pair transceiver as well as the link integrity test functions. The LAN91C96 is a true 10BASE-T single chip device able to interface to a system or a local bus. Support for direct-driven LEDs for installation and run-time diagnostics is provided. 802.3 statistics are gathered to facilitate network management ...
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... PCMCIA I/O ignores address lines A4-A15 and relies on the PCMCIA host, decoding for the slot. nROM/nPCMCIA, on LAN91C96, is left open with a pullup for LOCAL BUS mode. This pin is sampled at the end of RESET. If found low, the LAN91C96 is configured for PCMCIA mode. Rev. 03-28-07 ...
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... Uses non-volatile jumperless setup via serial EEPROM. The device must power up in LOCAL BUS mode with nIORD and nIOWR asserted simultaneously to make the controller enter the 68000 mode. Note: The first write to the 68000 configured controller must be a write. SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 9 DATASHEET Rev. 03-28-07 ...
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... VDD 100 2122 2728 29 30 Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet LAN91C96 100 Pin QFP Figure 3.1 - LAN91C96 100 Pin QFP Page 10 DATASHEET 50 VDD 49 A19/nCE1 48 A18 ...
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... INTR0/nIREQ/INTR 17 INTR1/nINPACK 18 VDD 19 INTR2 20 INTR3 21 VSS 22 nIOCS16/nIOIS16 23 nSBHE/nCE2 24 BALE/nWE 25 SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet LAN91C96 100 Pin TQFP Figure 3.2 - LAN91C96 100 Pin TQFP Page 11 DATASHEET 75 TPETXP 74 TPETXDN 73 TPETXN 72 TPETXDP 71 AVDD 70 nTXLED/nTXEN 69 nRXLED/RXCLK 68 nLNKLED/TXD 67 nBSELED/RXD 66 PWRDWN/TXCLK ...
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... PCMCIA CONNECTOR nWE nOE D0-7 A0-X SINGLE FUNCTION PCMCIA CARD WITH THE LAN91C96 Figure 3.3 - LAN91C96 System Block Diagram Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet nCE1, nCE2, nREG, nWE A0-9, A15 nIORD, nIOWR STSCHG RESET LAN91C96 nIREQ D0-15 nIOIS16, nINPACK nWAIT nOE ...
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... CABLE SIDE DIAGNOSTIC LEDs Figure 3.4 – System Diagram for Local Bus with Boot Prom SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet AUI Page 13 DATASHEET Rev. 03-28-07 ...
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... GND, AGND GND, AGND TPERXP TPERXP TPERXN TPERXN TPETXP TPETXP TPETXN TPETXN TPETXDP TPETXDP TPETXDN TPETXDN RECP RECN RECP RECN COLP COLN COLP COLN TXP/nCOLL TXP/nCOLL TXN/nCRS TXN/nCRS Page 14 DATASHEET MAX 68000 NUMBER OF PINS SMSC LAN91C965v&3v ...
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... FUNCTION LOCAL BUS LEDs nLNKLED/TXD nRXLED/RXCLK nBSELED/RXD nTXLED/nTXEN MISC. RBIAS PWRDWN/TX CLK nXENDEC nEN16 nROM SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet PCMCIA nLNKLED/TXD nLNKLED/TXD nRXLED/RXCLK nRXLED/RXCLK nBSELED/RXD nBSELED/RXD nTXLED/nTXEN nTXLED/nTXEN RBIAS RBIAS PWRDWN/TX PWRDWN/TXC CLK LK nXENDEC ...
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... I/O4 with This pin is sampled at the end of RESET. When this pullup pin is sampled low the LAN91C96 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For LOCAL BUS operation this pin is left open and it is used as a ROM chip select output that goes active when nMEMR is low and the address bus contains a valid ROM address ...
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... AEN is low and A4-A15 decode to the LAN91C96 address programmed into the high byte of the Base Address Register. PCMCIA - Active low output asserted whenever the LAN91C96 bit mode, COR0 bit is high and nREG is low. IS with LOCAL BUS, PCMCIA - Input. Active low read strobe pullup used to access the LAN91C96 IO space ...
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... EXTERNAL ENDEC - Receive clock input. pullup OD16 INTERNAL ENDEC - Link LED output. O162 EXTERNAL ENDEC - Transmit Data output. I with Input. This active high input enables the EEPROM to pullup be read or written by the LAN91C96. Internally pulled up. Must be connected to ground if no serial EEPROM ** is used. Page 18 DATASHEET SMSC LAN91C965v&3v ...
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... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet TYPE DESCRIPTION I with Input. When low the LAN91C96 is configured for 16 bit pullup bus operation. If left open the LAN91C96 works in 8 bit bus mode. 16 bit configuration can also be ** programmed via serial EEPROM or software initialization of the CONFIGURATION REGISTER. Iclk An external parallel resonance 20MHz crystal should be connected across these pins ...
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... Clock input buffer. ** Signal is 5.0V input tolerant when V DC levels and conditions defined in the DC Electrical Characteristics section. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet TYPE DESCRIPTION Ground pins. Analog ground pins. =3.3V. For Revision E and later. cc Page 20 DATASHEET SMSC LAN91C965v&3v ...
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... DATABU ADDRES BUS BUS INTERFAC CONTROL Figure 4.1 - LAN91C96 Internal Block Diagram SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet ARBITE CSMA/C MMU TWISTED TRANSCEIVE RAM Page 21 DATASHEET ENDE AUI 10BASE- Rev. 03-28-07 ...
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... It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision detection as well as the link integrity test function. The LAN91C96 provides a 16-bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. RAM memory is managed by the MMU ...
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... The LAN91C96 consists of an integrated Ethernet controller mapped entirely in I/O space. In addition, PCMCIA attribute memory space is decoded to interface an external CIS ROM, with configuration registers as per PCMCIA 3.X extensions (except COR) implemented on-chip in attribute space above the ROM decode area. The PCMCIA Configuration Registers are accessible in I/O space and also to allow non-PCMCIA dual function designs ...
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... Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 24 DATASHEET SMSC LAN91C965v&3v ...
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... Figure 5.2 – Transmit Queues and Mapping SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 25 DATASHEET Rev. 03-28-07 ...
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... Figure 5.3 – Receive Queues and Mapping Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 26 DATASHEET SMSC LAN91C965v&3v ...
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... INTERFACE Control Control 8-16 bit Bus Interface Address Control Unit WR FIFO Data RD FIFO Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Control Control Control Arbiter Ethernet Protocol Handler MMU TX/RX DMA FIFO ...
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... Figure 5.5 – Logical Address Generation and Relevant Registers Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 28 DATASHEET SMSC LAN91C965v&3v ...
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... This space also allows access to the PCMCIA Configuration Register through Bank 4. Table 5.2 - Bus Transactions In LOCAL BUS Mode 8 BIT MODE ((nEN16=1) (16BIT=0)) 16 BIT MODE otherwise SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Table 5.1 - LAN91C96 Address Space LOCAL PCMCIA 68000 BUS ...
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... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet NCE1 NCE2 D0 Even byte 0 X Odd byte Even byte 0 1 Even byte 0 1 Odd byte D0-7 ILLEGAL ACCESS Even byte Page 30 DATASHEET D8- CYCLE Odd byte - Odd byte NO CYCLE D8-15 Odd byte SMSC LAN91C965v&3v ...
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... IA, CONF and BASE registers. It does not reset any PCMCIA Configuration Register. 5.4 Power Down Logic States Table 5.6, Table 5.7, Table 5.8, and Table 5.9 describe the power down states of the LAN91C96. pins and bits involved in power down are: 1. PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0). 2. ...
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... LAN91C96 Power Down States Table 5.6 - LOCAL BUS Mode Defined States (Refer To Table 5.7 For Next States To Wake-Up Events) ECOR PWRDWN PIN NO. FUNCTION (A= ASSRTD) ENABLE Notes: The chart assumes that ECOR Function Enable bit is meaningless in LOCAL BUS mode. ...
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... Note : The LAN91C96 implementation is different from the LAN91C95; the LAN91C96 powers down the Ethernet Rx and Link logic also, whereas, the LAN91C95 does not. PWR DWN PIN NO. WAKES UP BY (A= ASSRTD) 1 PWRDWN Pin deassertion writing CTR WAKEUP_EN bit SMSC LAN91C965v& ...
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... LAN9xxx family of Ethernet LAN Controllers. The EEPROM is optional for both LOCAL BUS and PCMCIA requiring a Minimum size bit word addresses. The LAN91C96 generates the appropriate control lines (nFCS and nFWE) to read and write the Attribute memory, and it tri-states the data bus during external Attribute Memory accesses. Only even locations are used ...
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... LAN91C96 uses address A0-9, A15, along with nREG, nCE1, nWE and nOE odd byte address access (A0=1), the LAN91C96 will generate a arbitrary value of Zero (0) since the PCMCIA specification states that the high byte of a word access in attribute memory is a don’ ...
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... BIT 4 - Not defined BIT 3 - Not defined BIT 2 - PwrDwn: When set (1), this bit puts the LAN91C96 Ethernet function into power down mode. The Ethernet function is also put into power down mode when the Enable Function bit (ECOR bit 0 in PCMCIA only) is cleared. Refer to the Power Down Logic section for additional information. ...
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... BYTE COUNT WORD, the DATA AREA and the CONTROL BYTE. The receive byte count always appears as even, the ODDFRM bit of the receive status word indicates if the low byte of the last word is SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet ...
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... On transmit, all bytes are provided by the CPU, including the source address. The LAN91C96 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C96 treated transparently as data for both transmit and receive operations. ...
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... MULTCAST - Receive frame was multicast. If hash value corresponds to a multicast table bit that is set, and the address was a multicast, the packet will pass address filtering regardless of other filtering criteria. SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet HASH VALUE 5-0 ...
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... FIFO PORTS IA 0-1 IA 2-3 POINTER IA 4-5 DATA MGMT GENERAL DATA REVISION PURPOSE CONTROL INTERRUPT ERCV BANK SELECT REGISTER Figure 6.2 - LAN91C96 Registers Page 40 DATASHEET 16 Bit Registers BANK3 BANK4 ECOR (LOW BYTE) ECSR (HIGH BYTE) BANK SELECT BANK2 Register used during run time. SMSC LAN91C965v&3v ...
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... Some registers (e.g. the Interrupt Ack. or the Interrupt Mask) are functionally described as two eight bit registers. In such case, the offset of each one is independently specified. Regardless of the functional description, when the LAN91C96 bit mode, all registers can be accessed as words or bytes. RST Val - The default bit values upon hard reset are highlighted below each register. ...
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... This register is always accessible except in power down mode and is used to select the register bank in use. The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C96. The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. The LAN91C96 implements only 5 banks in both PCMCIA and LOCAL BUS mode, therefore accesses to non-existing banks will ignore writes and reads will return 0x33 on byte reads ...
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... When this bit is clear the transmitter ignores its own carrier. Defaults low. PAD_EN - When set, the LAN91C96 will pad transmit frames shorter than 64 bytes with 00. For TX, CPU should write the actual BYTE COUNT before padded by the LAN91C96 to the buffer RAM, excludes the padded 00 ...
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... TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C96 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. AUI FDSE FDUPLX ...
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... TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared by the start of a new frame transmission or when TXENA is set high. Fatal errors are: 16 collisions SQET fail and STP_SQET = 1 FIFO Underrun Carrier lost and MON_CSN = 1 Late collision SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 45 DATASHEET Rev. 03-28-07 ...
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... SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by writing the bit low. The LAN91C96 configuration is not preserved, except for Configuration, Base, and IA0- 5 Registers. The EEPROM in both LOCAL BUS and PCMCIA mode is not reloaded after software reset. ...
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... FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register defaults to the MEMORY SIZE upon reset or upon the RESET MMU command. MEMORY SIZE - This register can be read to determine the total memory size, and will always read 18H (6144 bytes) for the LAN91C96. LAN91C90 LAN91C90 ...
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... NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three 20MHz clocks on any cycle to the LAN91C96. FULL STEP - This bit is used to select the signaling mode for the AUI port. When set the AUI port uses full step signaling ...
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... A15 - A13 and These bits are compared in LOCAL BUS mode against the I/O address on the bus to determine the IOBASE for LAN91C96 registers. The 64k I/O space is fully decoded by the LAN91C96 down location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. ...
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... NAME READ/WRITE ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS Page 50 DATASHEET TYPE SYMBOL IAR SMSC LAN91C965v&3v ...
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... PWRDN - Active high bit used to put the Ethernet function in power down mode. Cleared by write to any register in the LAN91C96 I/O space. 2. Hardware reset. This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down. ...
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... During this time, attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the LAN91C96 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750usec in either mode. ...
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... C) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER. SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet NAME TYPE WRITE ONLY ...
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... LAN91C96 dual ported RAM. In the case of the AutoTx bit being cleared, the host must manually start the transmit operation. When the AutoTx bit is set, the EPH Transmit engine compares the number of bytes moved into the transmit packet buffer with the value of the Auto TX Start Register to start transmit operation ...
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... Interrupt Status Register. TOP OF RX FIFO PACKET NUMBER - Packet number presently at the output of the RX FIFO. Only valid if REMPTY is clear. The packet is removed from the RX FIFO using MMU Commands 6) or 8). SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet NAME ...
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... The loading operation proceeds in parallel with the transmission, and in the case that the transmitter gets ahead of the CPU, the LAN91C94 will prevent the transmission of erroneous data by forcing an Underrun condition. Underruns will be triggered by starving the transmit DMA if the LAN91C96 detects that the DMA TX address exceeds the pointer address.” ...
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... DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer register. This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO ...
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... INT MASK MASK MASK Page 58 DATASHEET TYPE SYMBOL READ ONLY IST TX EMPTY INT TX INT RCV INT TYPE SYMBOL WRITE ONLY ACK TX EMPTY INT TX INT TYPE SYMBOL READ/WRITE MSK TX EMPTY INT TX INT RCV INT MASK MASK MASK SMSC LAN91C965v&3v ...
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... FIFO empty is desired, the bit should be first cleared and then read. The TX_EMPTY MASK bit should only be set after the following steps packet is enqueued for transmission SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 59 DATASHEET ...
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... Notes: For edge triggered systems, the Interrupt Service Routine should clear the Interrupt Mask Register, and only enable the appropriate interrupts after the interrupt source is serviced (acknowledged). Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 60 DATASHEET SMSC LAN91C965v&3v ...
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... TX FIFO Not Empty SMSC LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Figure 7.1 – Interrupt Structure Page 61 DATASHEET Rev. 03-28-07 ...
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... Multicast Table Multicast Table NAME READ/WRITE nXNDEC IOS2 1 1 MDOE MCLK Page 62 DATASHEET TYPE SYMBOL TYPE SYMBOL MGMT IOS1 IOS0 MDI MD0 SMSC LAN91C965v&3v ...
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... CHIP - Chip ID. Can be used by software drivers to identify the device used. REV - Revision ID. Incremented for each revision of a given device. Note 7.2 The LAN91C96 shares the same chip ID (#4) as the LAN91C94. The Rev. ID for the LAN91C96 will begin from six (#6). SMSC DS – LAN91C965v&3v ...
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... Counter register will return a value of “0” when no receive event is occurring. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet NAME EARLY RCV REGISTER RCV COUNTER ERCV THRESHOLD Page 64 DATASHEET TYPE SYMBOL READ/WRITE ERCV SMSC LAN91C965v&3v ...
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... This mode is enabled using the FDUPLX bit in the TCR. In this mode the CSMA/CD algorithm is used to gain access to the media. 2. FDSE (Full Duplex Switched Ethernet). Enabled by FDSE bit in TCR bit. When the LAN91C96 is configured for FDSE, its transmit and receive paths will operate independently with Carrier Sense CSMA/CD function disabled. ...
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... When a magic packet is received, the Ethernet controller will generate an interrupt causing the host to initiate a service routine to find the source of the event. The Interrupt bit in the ECSR is also set if the host plans on polling the controller for Wakeup status. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 66 DATASHEET SMSC LAN91C965v&3v ...
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... TX FIFO. The transmission is now enqueued. No further CPU intervention is needed until a transmit interrupt is generated SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state ...
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... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet MAC SIDE The enqueued packet will be transferred to the MAC block as a function of TXENA (nTCR) bit and of the deferral process (1/2 duplex mode only) state. Transmit pages are released by transmit completion. Page 68 DATASHEET SMSC LAN91C965v&3v ...
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... CPU issues the REMOVE AND RELEASE FROM TOP OF RX command to have the MMU free up the used memory and packet number. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet a) The MAC generates a TXEMPTY interrupt upon a completion of a sequence of enqueued packets ...
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... Figure 8.1 – Interrupt Service Routine Page 70 DATASHEET Yes RX INTR? Call RXINTR Yes Write Allocated Pkt# into Packet Number Reg. Write Ad Ptr Reg. & CopyData & Source Address Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Disable Allocation Interrupt Mask SMSC LAN91C965v&3v ...
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... SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet RX INTR Write Ad. Ptr. Reg. & Read Word 0 from RAM Destination Yes No Multicast? Read Words from RAM for Address Filtering No Yes Address Filtering Pass? No Yes Status Word OK? Do Receive Lookahead ...
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... Step 4.2.3 // Option 1: Release the packet Write (0x00A0, (Bank2, Offset 0)); //Option 2: Re-Enqueue the packet Write (0x00C0, (Bank2, Offset 0)); Step 4.2.4: Re-Enable Transmission Temp = Read(Bank0, Offset 0); Temp = Temp2 OR 0x0001 Write (Temp2, (Bank 0, Offset 0)); Step 4.2.5: Return from the routine Figure 8.3 -TX INTR Page 72 DATASHEET SMSC LAN91C965v&3v ...
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... TXEMPTY = 0 & TXINT = 0 (Waiting for Completion) SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet TXEMPTY INTR Write Acknowledge Reg. with TXEMPTY Bit Set Read TXEMPTY & TX INTR TXEMPTY = X & TXINT = 1 (Everything went through (Transmission Failed) Read Pkt. # Register & Save ...
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... RAM Write Source Address into Proper Location Copy Remaining TX Data Packet into RAM Enqueue Packet Set "Ready for Packet" Flag Return Buffers to Upper Layer Return Page 74 DATASHEET No Store Data Buffer Pointer Clear "Ready for Packet" Flag Enable Allocation Interrupt SMSC LAN91C965v&3v ...
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... If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the LAN91C96, the CPU can dynamically program this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more memory to be allocated for receive (by reducing the value of the reserved memory) ...
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... Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines. POWER DOWN The LAN91C96 can enter power down mode by means of the PWRDWN pin (pin 68) or the PWRDN bit (Control Register, bit 13). When in power down mode, the LAN91C96 will: Stop the crystal oscillator Tristate: Data Bus − ...
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... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet PWRDN BIT 0 Normal external ENDEC operation 0 Normal internal ENDEC operation 0 Powerdown - Normal mode restored by PWRDWN pin going low Powerdown - Bit is cleared by a write 1 access to any LAN91C96 register or by hardware reset Page 77 DATASHEET Rev. 03-28-07 ...
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... Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 78 DATASHEET SMSC LAN91C965v&3v ...
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... The arbiter uses the pointer register as the CPU provided address, and the internal DMA address from the CSMA/CD side as the addresses to be provided to the MMU. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet ...
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... For LOCAL BUS, I/O address decoding is done by comparing A15-A4 to the I/O BASE address determined in part by the upper byte of the BASE ADDRESS REGISTER, and also requiring that AEN be low. If the above address comparison is satisfied and the LAN91C96 bit mode, nIOCS16 will be asserted (low). ...
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... Data Register. For example LOCAL BUS system the cycle time bit transfer will be at least 2 clocks for the I/O access to the LAN91C96 (+ one clock for the memory cycle) for a total of 3 clocks. In absolute time it means 375ns for an 8MHz bus, and 240ns for a 12 ...
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... Register. The CPU can remove a packet number from this FIFO by issuing a TX INT acknowledge. The CPU can determine if this FIFO is empty by reading the TX INT bit or the FIFO Ports Register. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 82 DATASHEET SMSC LAN91C965v&3v ...
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... The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the LAN91C96 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths ...
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... Collisions on same frame 2. Late collision 3. Lost Carrier sense and MON_CSN set 4. Transmit Underrun 5. SQET error and STP_SQET set Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 84 DATASHEET SMSC LAN91C965v&3v ...
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... The address filtering is done inside the CSMA/CD block. A packet will be received if the destination address is broadcast addressed to the individual address of the LAN91C96 multicast address and ALMUL bit is set multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received ...
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... Link_test_max_timer The state of the link is reflected in the EPHSR. 9.11 AUI The LAN91C96 also provides a standard six wire AUI interface to a coax transceiver. 9.12 Physical Interface The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver. The ENDEC also provides a standard 6-pin AUI interface to an external coax transceiver for 10BASE-2 and 10BASE-5 applications ...
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... If the input signal exceeds the squelch requirements, the carrier sense output, nCRS, is asserted. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 87 DATASHEET Rev ...
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... The Link Integrity function can be disabled for pre-10BASE-T twisted-pair networks. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Page 88 DATASHEET SMSC LAN91C965v&3v ...
Page 89
... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the LAN91C96. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ROM BASE, INTERRUPT) that can always be used regardless of the EEPROM based value being programmed ...
Page 90
... Notice that the chip is required to power up in LOCAL BUS mode to use the 68000 interface. For the first chip access, the first transfer (to the LAN91C96) must be a write. The LAN91C96 uses this write to confirm the 68000 mode. An attempted read may return incorrect data. The LAN91C96 responds to addresses per the base address register contents (as in LOCAL BUS mode) ...
Page 91
... DATA to DATA (Upper and lower bytes swapped) Interrupt (if used) to INT0 The following signals MUST be pulled as stated: LAN91C96 Address bit 0 tied low LAN91C96 nSBHE input tied low All INTx must have a 1KΩ to 10KΩ pull-up to keep the line high while the drivers are tri-stated. ...
Page 92
... Schmitt Trigger Hysteresis Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet * = +3.3 V ± 10% as noted for Revisions E and later) CC SYMBOL MIN TYP = 5.0V V ILI V 2.0 IHI V ILIS V 2.2 IHIS V 250 HYS Page 92 DATASHEET + 0.3V CC MAX UNITS COMMENTS 0.8 V TTL Levels V 0.8 V Schmitt Trigger V Schmitt Trigger mV SMSC LAN91C965v&3v ...
Page 93
... Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage Input Current for Type Buffers Input Current SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet SYMBOL MIN TYP V ILCK V 3.3 IHCK = 3.3V (Revisions E and later) ...
Page 94
... OH µ - µ - µ µ SMSC LAN91C965v&3v ...
Page 95
... Low Output Level High Output Level Output Leakage O4 Type Buffer Low Output Level High Output Level Output Leakage OD16 Type Buffer Low Output Level Output Leakage SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet SYMBOL MIN TYP MAX V 0 ...
Page 96
... µ µA + All outputs open All outputs open @2.4V mA @0.4V UNIT TEST CONDITION pF All pins except pin under test tied to AC ground SMSC LAN91C965v&3v ...
Page 97
... Transmitter Backswing Voltage to Idle Input Differential Voltage Output Short Circuit ( GND) Current CC Differential Idle Voltage (measured 8.0 µs after last positive transition of data frame) SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet MIN TYP 10BASE-T 100 300 ...
Page 98
... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet MIN TYP 10BASE-T TBD 225 260 0 +/- 1.3 +/- 1.5 +/- 0.520 AUI TBD 120 140 0 +/- 0.39 +/- 0.47 +/- 0.25 240 pF 120 Page 98 DATASHEET MAX UNITS mV 520 mV Vdd +/- 1 ohms 50 mV 100 mV +/- 160 mV Vdd +/- 0.55 V 100 mV +/- 0.990 V TBD SMSC LAN91C965v&3v ...
Page 99
... Address, nREG Hold after Control Inactive t64 nCE1 Setup to nWE Rising t65 nCE1 Low to Valid Data Figure 12.1 – Card Configuration Registers – Read/Write PCMCIA Mode (A15=1) SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t63 t62 t63 t57 ...
Page 100
... Figure 12.2 – Local Bus Consecutive Read Cycles Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID ADDRESS t4 t20 VALID DATA OUT Parameter min 10 20 185 Page 100 DATASHEET Z VALID DATA OUT typ units max SMSC LAN91C965v&3v ...
Page 101
... Hold after Control Inactive t51 Address Setup to Control Active t52 Address Hold after Control Inactive t53 nIORD Active to Data Valid Figure 12.3 - PCMCIA Consecutive Read Cycles SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t52 valid t49 t50 t20 t53 ...
Page 102
... Figure 12.4 – Local Bus Consecutive Write Cycles Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t4 t20 t8 t7 VALID DATA IN Parameter min 185 Page 102 DATASHEET VALID ADDRESS VALID DATA typ max units SMSC LAN91C965v&3v ...
Page 103
... Cycle Time (No Wait States) Write Data Setup to nIOWR Rising t54 Write Data Hold after nIOWR Rising t55 Figure 12.5 - PCMCIA Consecutive Write Cycles SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t52 valid t49 t50 t20 t54 ...
Page 104
... Figure 12.6 – Local Bus Consecutive Read and Write Cycles Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t20 Z t10 Z VALID DATA Parameter min 100 185 Page 104 DATASHEET VALID ADDRESS Z VALID DATA typ max units 12 ns 150 ns ns SMSC LAN91C965v&3v ...
Page 105
... IOCHRDY is used instead of meeting t20 and t43. "No Wait St' bit IOCHRDY only negated if needed and only for Data Register access. Figure 12.7 – Data Register Special Read Access SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID ADDRESS ...
Page 106
... Wait St' bit IOCHRDY only negated if needed and only for Data Register access. Figure 12.8 – Data Register Special Write Access Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID ADDRESS t9 t18 VALID DATA IN Parameter min Page 106 DATASHEET Z typ max units 15 ns 425 ns SMSC LAN91C965v&3v ...
Page 107
... Z D0-7 t3 Address, nSBHE, AEN Setup to Control Active t5 nIORD Low to Valid Data t7 Data Setup to nIOWR Rising t8 Data Hold after nIOWR Rising SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID ADDRESS Z VALID DATA OUT Parameter min Figure 12.9 - 8-Bit Mode Register Cycles ...
Page 108
... Page 108 DATASHEET COMMENTS R/nW asserted before nAS nAS assertion time Address setup time Address hold time nAS to xDS deassertion delay xDS assertion time Data setup time (Access time) Data hold time Consecutive reads cycle time SMSC LAN91C965v&3v ...
Page 109
... SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t3 t10 Figure 12.11 - 68000 Write Timing MAX UNIT nsec R/nW assertion before nAS nsec nAS assertion time ...
Page 110
... High to nROM High(Internal) BALE tied high Figure 12.12 – External ROM Read Access Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet ADDRESS VALID min Page 110 DATASHEET t4 t17 typ max units SMSC LAN91C965v&3v ...
Page 111
... A4-A15, AEN Low, BALE High to nIOCS16 Low t5 BALE Pulse Width t4 not needed. nIOCS16 not relevant in 8-bit mode. Figure 12.13 – Local Bus Register Access When Using Bale SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID ...
Page 112
... High to nROM High Figure 12.14 – External ROM Read Access Using Bale Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet VALID t2 t3 t16 Page 112 DATASHEET t17 ty p max unit SMSC LAN91C965v&3v ...
Page 113
... EEDO EEDI EECS t21 t21 EESK Falling to EECS Changing t68 EESK Falling to EEDO Changing 9346 is typically the serial EEPROM used. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t68 Parameter min 0 Figure 12.15 - EEPROM Read Page 113 DATASHEET ...
Page 114
... EESK Falling to EECS Changing t70 EESK Falling to EEDO Changing 9346 is typically the serial EEPROM used. Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t70 Parameter min Figure 12.16 - EEPROM Write Page 114 DATASHEET t69 typ max units SMSC LAN91C965v&3v ...
Page 115
... Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) nTXEN TXD TXCLK t22 t22 TXD, nTXEN Delay from TXCLK Falling Figure 12.18 – External ENDEC Interface – Start of Transmit SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t67 t67 t67 t67 t67 t66 ...
Page 116
... RXD Hold after RXCLK Falling Figure 12.19 – External ENDEC Interface – Receive Data Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t23 t24 t23 min typ 10 30 (RXD SAMPLED BY FALLING RXCLK) Page 116 DATASHEET max units ns ns SMSC LAN91C965v&3v ...
Page 117
... TPETXP(N) to TPETXDP(N) Delay t33 TPETXDN to TPETXDP Skew t34 TXP to TXN Skew Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t31 t32 t32 t33 t33 TWISTED PAIR DRIVERS ...
Page 118
... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t35 first bit decoded t36 t37 t38 Parameter min 450 Page 118 DATASHEET first bit decoded typ max units 100 500 550 ns SMSC LAN91C965v&3v ...
Page 119
... TPERXP TPERXN RECP RECN nCRS (internal) t39 Receiver Turn Off Delay Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T) SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet last bit 1/0 t39 Parameter min 200 Page 119 ...
Page 120
... Transmit Output High before Idle in Half-Step Mode Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T) Rev. 03-28-07 Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet t40 t41 last bit a 1/0 Parameter min 200 Page 120 DATASHEET typ max units 800 ns ns SMSC LAN91C965v&3v ...
Page 121
... Pointer Register Reloaded to a Word of Data Prefetched into Data Register Note: If t44 is not met, IOCHRDY will be negated for the required time. This parameter can be ignored if IOCHRDY is connected to the system. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Parameter min Figure 12.24 – ...
Page 122
... Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Figure 12.26 – Input Clock Timing MIN 30/20 19.7 1 DATA t45 min 2 * t20 Figure 12.27 – Memory Write Timing Page 122 DATASHEET t F TYP MAX UNITS 50 ns 20/ msec 20.3 MHz 3 Meg Ohm POINTER REGISTER typ max units ns SMSC LAN91C965v&3v ...
Page 123
... Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet Figure 12.28 - 100 PIN QFP Package MAX 3 ...
Page 124
... Overall Package Height 0.15 1.05 16.20 14.10 16.20 14.10 0.20 Lead Frame Thickness 0. 0.27 ~ 0.20 0.08 Page 124 DATASHEET REMARKS Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity SMSC LAN91C965v&3v ...
Page 125
... I/O Space – Bank 2/ Top of RX FIFO Packet Number 20 Buffer Symbols 92 DC Electrical Characteristics 99 Timing Diagrams SMSC DS – LAN91C965v&3v Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet CORRECTION Added lead-free ordering information Modified Supply Current in power down mode Modified descriptions of Magic Packet Support ...