SP37E760-MD Standard Microsystems, SP37E760-MD Datasheet

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SP37E760-MD

Manufacturer Part Number
SP37E760-MD
Description
Manufacturer
Standard Microsystems
Datasheet

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The SMSC SP37E760 is a 3.3v PC 97-compliant I/O Controller. The SP37E760 utilizes SMSC’s proven SuperCell
technology and is optimized for embedded applications. The SP37E760 incorporates a 16-byte data FIFO, two
16C550 compatible UARTs and one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support.
Both on-chip UARTs are compatible with the NS16C550.
The parallel port is compatible with IBM PC/AT architectures. The parallel port ChiProtect circuitry prevents damage
caused by an attached powered printer when the SP37E760 is not powered.
The SP37E760 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down
modes. The SP37E760 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable
system configuration of key functions such as the parallel port, and UARTs.
SMSC DS – SP37E760
3.3 Volt Operation
Intelligent Auto Power Management
16 Bit Address Qualification (Optional)
Serial Ports
-
-
-
-
ISA Host Interface
General Purpose Address Decoder
-
Two High Speed NS16C550 Compatible
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
16-Byte Block Decode
UARTs with Send/Receive 16 Byte FIFOs
for Embedded Applications
3.3V I/O Controller
SP37E760-MD for 100 Pin TQFP Package
SP37E760-MC for 100 Pin QFP Package
ORDERING INFORMATION
GENERAL DESCRIPTION
FEATURES
Order Numbers:
S
S
Multi-Mode Parallel Port with ChiProtect
-
-
Bi-directional Parallel Port
-
-
-
-
-
100 Pin QFP and TQFP Packages
Standard Mode
IBM PC/XT, PC/AT, and PS/2 Compatible
Enhanced Parallel Port (EPP) Compatible
EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
Enhanced Capabilities Port (ECP) Compatible
(IEEE 1284 Compliant)
Incorporates ChiProtect Circuitry for Protection
Against Damage Due to Printer Power-On
192 Base I/O Address, 7 IRQ and 3 DMA Options
PRELIMINARY
SP37E760
Rev. 04/13/2001

Related parts for SP37E760-MD

SP37E760-MD Summary of contents

Page 1

... Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 7 IRQ and 3 DMA Options 100 Pin QFP and TQFP Packages S GENERAL DESCRIPTION ORDERING INFORMATION Order Numbers: SP37E760-MC for 100 Pin QFP Package SP37E760-MD for 100 Pin TQFP Package SP37E760 PRELIMINARY Rev. 04/13/2001 ...

Page 2

... OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – SP37E760 Page 2 Rev. 04/13/2001 ...

Page 3

... EPP 1.9 OPERATION................................................................................................................... 30 5.2.1 Software Constraints ............................................................................................................. 30 5.2.2 EPP 1.9 Write ........................................................................................................................ 30 5.2.3 EPP 1.9 Read........................................................................................................................ 31 5.3 EPP 1.7 OPERATION................................................................................................................... 31 5.3.1 Software Constraints ............................................................................................................. 31 5.3.2 EPP 1.7 Write ........................................................................................................................ 31 5.3.3 EPP 1.7 Read........................................................................................................................ 32 5.4 EXTENDED CAPABILITIES PARALLEL PORT ........................................................................... 33 5.4.1 Vocabulary ............................................................................................................................ 33 5.4.2 ISA IMPLEMENTATION STANDARD................................................................................... 34 5.4.3 Description ............................................................................................................................ 34 5.4.4 Register Definitions ............................................................................................................... 35 5.4.5 OPERATION ......................................................................................................................... 39 SMSC DS – SP37E760 TABLE OF CONTENTS ........................................................................................................ 14 ................................................................................................ 23 PERATION .................................................................................................... 23 O ........................................................................... 25 ODE PERATION Page 3 Rev. 04/13/2001 ...

Page 4

... CR10 ..................................................................................................................................... 53 7.3.18 CR11 ..................................................................................................................................... 53 7.3.19 CR12 - CR13......................................................................................................................... 54 7.3.20 CR14 ..................................................................................................................................... 54 7.3.21 CR15 ..................................................................................................................................... 54 7.3.22 CR16 ..................................................................................................................................... 54 7.3.23 CR17 ..................................................................................................................................... 54 7.3.24 CR18 - CR1D ........................................................................................................................ 54 7.3.25 CR1E ..................................................................................................................................... 55 7.3.26 CR1F ..................................................................................................................................... 55 7.3.27 CR20 ..................................................................................................................................... 55 7.3.28 CR21 - CR22......................................................................................................................... 55 7.3.29 CR23 ..................................................................................................................................... 55 7.3.30 CR24 ..................................................................................................................................... 55 7.3.31 CR25 ..................................................................................................................................... 55 7.3.32 CR26 ..................................................................................................................................... 56 7.3.33 CR27 ..................................................................................................................................... 56 7.3.34 CR28 ..................................................................................................................................... 56 7.3.35 CR29 ..................................................................................................................................... 57 7.3.36 CR2A ..................................................................................................................................... 57 7.3.37 CR2B ..................................................................................................................................... 57 7.3.38 CR2C..................................................................................................................................... 57 7.3.39 CR2D..................................................................................................................................... 58 7.3.40 CR2E ..................................................................................................................................... 58 7.3.41 CR2F ..................................................................................................................................... 58 8 OPERATIONAL DESCRIPTION ......................................................................................................... 59 SMSC DS – SP37E760 .......................................................................................................... 43 P ..................................................................................................... 45 ORTS D ...................................................................................... 46 ESCRIPTION Page 4 Rev. 04/13/2001 ...

Page 5

... MAXIMUM GUARANTEED RATINGS ......................................................................................... 59 8.2 DC ELECTRICAL CHARACTERISTICS ...................................................................................... TIMING .......................................................................................................................................... 62 9 .................................................................................................................................. 62 OST IMING 9 ...................................................................................................................... 65 ERIAL ORT IMING 9 .................................................................................................................. 66 ARALLEL ORT IMING 9.3.1 Parallel Port EPP Timing....................................................................................................... 67 9.3.2 Parallel Port ECP Timing....................................................................................................... 71 10 PACKAGE OUTLINES .................................................................................................................... 76 11 SP37E760 REVISIONS ................................................................................................................... 78 SMSC DS – SP37E760 Page 5 Rev. 04/13/2001 ...

Page 6

... ADRX/IRQ_B 94 95 VSS nDACK_C 96 97 A10 98 IRQIN 99 DRQ_C IOCHRDY 100 FIGURE 1 - SP37E760 QFP PIN CONFIGURATION SMSC DS – SP37E760 SP37E760 100 PIN QFP 24 25 Page VSS 46 AEN ...

Page 7

... ADRX/IRQ_B 92 VSS 93 nDACK_C 94 A10 95 IRQIN 96 DRQ_C 97 IOCHRDY 100 1011121314151617 1819202122 23 2425 FIGURE 2 - SP37E760 TQFP PIN CONFIGURATION SMSC DS – SP37E760 SP37E760 100 PIN TQFP Page 7 DRQ_B VSS 45 AEN 44 nIOW 43 nIOR 42 ...

Page 8

... Reset 98 100 I/O Channel Ready (Note 86 88 Receive Data 2 SMSC DS – SP37E760 BUFFER SYMBOL TYPE HOST PROCESSOR INTERFACE D0-D7 IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. ...

Page 9

... Terminal Ready 80,90 82,92 nClear to Send 78,88 80,90 nData Set Ready 83,85 85,87 nData Carrier Detect SMSC DS – SP37E760 BUFFER SYMBOL TYPE TXD2 O12PD Transmit serial data output for port 2. RXD1 I Receiver serial data input for port 1. TXD1 O12 Transmit serial data output for port 1. nRTS1 O6 Active low Request to Send outputs for the Serial Port ...

Page 10

... Busy 60 62 nAcknowl- edge 58 60 Paper End SMSC DS – SP37E760 BUFFER SYMBOL TYPE nRI1 I Active low Ring Indicator inputs for the serial port. 1 Handshake signal which notifies the UART that the (Note ) telephone ring signal is detected by the modem. The ...

Page 11

... Non Connect 16, 21, 24, 10, 11, 18, 99, 100 23, 26, SMSC DS – SP37E760 BUFFER SYMBOL TYPE SLCT This high active output from the printer indicates that I/OD12 it has power on. Bit 4 of the Printer Status Register reads the SLCT input. ...

Page 12

... Output Drivers Active output drivers in the SP37E760 will always achieve the minimum specified DC Electrical Characteristics shown in Table 54. Note: If there is a pull- external node driven by an active output driver the SP37E760 will sink current from the pull-up through the low impedance source. ...

Page 13

... IRQIN IOCHRDY SMSC DS – SP37E760 Vss (4) PWRGD POWER MANAGEMENT CONTROL BUS CONFIGURATION REGISTERS DATA BUS CLOCK GEN 14.318 CLOCK FIGURE 3 - SP37E760 BLOCK DIAGRAM Page 13 nACK MULTI-MODE nSLCTIN PARALLEL nINIT PORT nAUTOFD nSTROBE BUSY nACK , PE nERROR PD0, PD1, PD2 PD3, PD4 PD5, PD6, PD7 ...

Page 14

... Base +[400:403] for ECP Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 45 for more information. All logical blocks in the SP37E760 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks. ...

Page 15

... Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the SP37E760. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ...

Page 16

... Reserved, Bits Bits are RESERVED. Reserved bits cannot be written and return 0 when read. 4.1.4.5 FIFOs Enabled, Bits The FIFOs Enabled bits are set when the FIFO CONTROL Register bit 0 equals 1. SMSC DS – SP37E760 Page 16 Rev. 04/13/2001 ...

Page 17

... Setting the XMIT FIFO Reset bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self-clearing. SMSC DS – SP37E760 Table 5 - Interrupt Control INTERRUPT SET AND RESET FUNCTIONS ...

Page 18

... The Stop Bits bit specifies the number of stop bits in each transmitted or received serial character. Table 8 describes the Stop Bits encoding. Note: The receiver ignores stop bits beyond the first, regardless of the number of stop bits used in transmitting. SMSC DS – SP37E760 Table 6 - RCVR Trigger Encoding RCVR ...

Page 19

... The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM Control inputs (nDSR, nCTS, RI and DCD) respectively. 6. The Modem Control output pins are forced inactive. 7. Data that is transmitted is immediately received. SMSC DS – SP37E760 When bit 1 is set to a logic “1”, the Page 19 Rev. 04/13/2001 ...

Page 20

... Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is read-only. SMSC DS – SP37E760 Page 20 Rev. 04/13/2001 ...

Page 21

... PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES The internal Baud Rate Generator (BRG) using the Programmable Baud Rate Generator Divisor Latches DDL and DDM (Address Offset = 0 and 1, DLAB = 1, READ/WRITE) is capable of taking any clock input ( MHz) and SMSC DS – SP37E760 Page 21 Rev. 04/13/2001 ...

Page 22

... Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) SMSC DS – SP37E760 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 2307 0.03 1538 0.03 1049 0.005 858 ...

Page 23

... Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: SMSC DS – SP37E760 RESET CONTROL RESET ...

Page 24

... BIT 3 Data Bit 2 Data Bit 3 Data Bit 2 Data Bit 3 Enable Enable Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) SMSC DS – SP37E760 REGISTER SYMBOL BIT 0 RBR Data Bit 0 (Note 1) THR Data Bit 0 IER Enable Received Data Available Interrupt (ERDAI) IIR ” ...

Page 25

... UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun SMSC DS – SP37E760 BIT 4 ...

Page 26

... Rx FIFO within 4 character times of the last byte. The time-out interrupt is cleared or reset when the CPU reads the Rx FIFO or another character enters it. These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher baud rate capability (256K baud). SMSC DS – SP37E760 Page 26 Rev. 04/13/2001 ...

Page 27

... PARALLEL PORT The SP37E760 incorporates an IBM XT/AT compatible parallel port. The SP37E760 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the SP37E760 Configuration Registers and the following hardware configuration description for information on disabling, powering down, changing the base address, and selecting the mode of operation of the parallel port ...

Page 28

... The complement of the level on the nBUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic “1” means that it is ready to accept the next character. SMSC DS – SP37E760 Page 28 Rev. 04/13/2001 ...

Page 29

... EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. SMSC DS – SP37E760 Page 29 When the Rev. 04/13/2001 ...

Page 30

... Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. Chip may modify nWRITE and nPDATA in preparation for the next cycle. SMSC DS – SP37E760 beginning of the termination phase. Page 30 Rev. 04/13/2001 ...

Page 31

... If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 6. When the host deasserts nI0W the chip deasserts nDATASTB or nADDRSTRB and latches the data from the SData bus for the PData bus. SMSC DS – SP37E760 PData bus for the SData bus, deasserts the SData bus and asserts (releases) Page 31 ...

Page 32

... Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required low. SMSC DS – SP37E760 Table 15 - EPP Pin Descriptions TYPE DESCRIPTION O This signal is active low ...

Page 33

... MODE 1 Note These registers are available in all modes. 2 Note All FIFOs use one common 16 byte FIFO. SMSC DS – SP37E760 Table 16 - ECP Registers PD6 PD5 PD4 Address or RLE field nAck PError Select 0 Direction ackIntEn Parallel Port Data FIFO ...

Page 34

... I (nPeriphRequest) NInit O NSelectIn O SMSC DS – SP37E760 Table 17 - ECP Pin Descriptions DESCRIPTION During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). Contains address or data or RLE data. Indicates valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in reverse ...

Page 35

... ECP port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direction (direction is 0). Refer to the ECP Parallel Port Forward Timing Diagram, located in the Timing Diagrams section of this data sheet . 5.4.4.2 DEVICE STATUS REGISTER (dsr) ADDRESS OFFSET = 01H SMSC DS – SP37E760 Table 18 - ECP Register Definitions ECP MODES 000-001 011 All ...

Page 36

... Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). 5.4.4.3.7 Bits 6 and 7 during a read are a low level, and cannot be written. 5.4.4.4 cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 SMSC DS – SP37E760 enable interrupt requests from the Page 36 Rev. 04/13/2001 ...

Page 37

... This bit is read only. During a read low level. This means that this chip does not support hardware RLE compression. It does support hardware de-compression! 5.4.4.8.2 BIT 6 intrValue Returns the value on the ISA iRq line to determine possible conflicts. 5.4.4.8.3 BITS 5:0 Reserved During a read are a low level. These bits cannot be written. SMSC DS – SP37E760 Page 37 Rev. 04/13/2001 ...

Page 38

... Parallel Port FIFO mode. This is the same as 000 except that bytes are written or DMAed to the FIFO. FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is only useful when direction is 0. All drivers have active pull-ups (push-pull). SMSC DS – SP37E760 Table 20 - Extended Control Register MODE Page 38 Rev ...

Page 39

... ECP read data byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long not empty . ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. SMSC DS – SP37E760 MODE Page 39 Rev. 04/13/2001 ...

Page 40

... Table 21 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data Compression The SP37E760 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo. ...

Page 41

... If PDRQ goes inactive due to the FIFO going empty, then PDRQ is active again as SMSC DS – SP37E760 nd cycle, PDRQ must be kept unasserted until nPDACK ...

Page 42

... FIFO this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16- <threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO. SMSC DS – SP37E760 it can be emptied completely in a single burst, otherwise readIntrThreshold Page 42 ...

Page 43

... SYSTEM INTERFACE PINS Table 22 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the SP37E760 when they have indeterminate input values. ...

Page 44

... SPP, PS/2 Parallel port or EPP mode is selected through ecr while in ECP mode. The parallel port logic can change powerdown modes when the ECP mode is changed through the ecr register or when the parallel port mode is changed through the configuration registers. SMSC DS – SP37E760 Page 44 Rev. 04/13/2001 ...

Page 45

... EXITING THE CONFIGURATION STATE To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The SP37E760 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. ...

Page 46

... CONFIGURATION SELECT REGISTER (CSR) The Configuration Select Register can only be accessed when the SP37E760 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT. ...

Page 47

... CR27 00H CR28 00H CR29 Reserved 00H CR2A 00H CR2B 00H CR2C 03H CR2D 00H CR2E 00H CR2F SMSC DS – SP37E760 DB6 DB5 DB4 DB3 Reserved Reserved ARDA6 ADRA5 ADRA4 0 Reserved Reserved Reserved UART 1 UART 2 Mode Speed Device ID Device Revision ...

Page 48

... To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. SMSC DS – SP37E760 Table 25 - CR00 DESCRIPTION Read Only ...

Page 49

... IRQ_B 1 2 Note : See Note in section CR05 on page 50. SMSC DS – SP37E760 Table 27 - CR02 DESCRIPTION Read Only. A read returns “0” high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. ...

Page 50

... The default value after power up is 00H . 7.3.7 CR06 (Reserved). The default value of this register after power up is FFH. SMSC DS – SP37E760 DESCRIPTION Bit 0 If CR1 bit low level then: 0 Standard and Bi-directional Modes (SPP) (default) 1 EPP Mode and SPP ...

Page 51

... ADRx Address Decoder (Table 33). Table 32 - CR09: ADRx Upper Address Decoder and Configuration D7 D6 ADRx CONFIGURATION CONTROL SMSC DS – SP37E760 DESCRIPTION Read as 0. Read as 0. Read as 0. This bit controls the AUTOPOWER DOWN feature of the Parallel Port. The function is Auto powerdown disabled (default Auto powerdown enabled This bit is reset to the default state by POR or a hardware reset ...

Page 52

... UART 2 RCV 1 UART 2 XMIT 2 UART 2 Duplex This bit is used to define the FULL/HALF DUPLEX UART 2 MODE UART 2 Mode 6 UART 1 Speed This bit enables the high speed mode of UART 1. SMSC DS – SP37E760 Table 33 - ADRx Configuration Bits ADRx CONTROL DESCRIPTION ADRx disabled ...

Page 53

... CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the SP37E760 Device ID. The default value of this register after power up is 28H. 7.3.15 CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only ...

Page 54

... LSB 7.3.23 CR17 (Reserved). The default value of this register after power up is 003H. 7.3.24 CR18 - CR1D CR18 - CR1D registers are Reserved and Read Only . The default value of these registers after power up is 00H. SMSC DS – SP37E760 Table 38 - CR11 BIT NAME DESCRIPTION Test 16 Test 17 ...

Page 55

... Serial Port 2 can be set to 96 locations on 8-byte boundaries from 100H - 3F8H. To disable Serial Port 2, set ADR9 and ADR8 to zero. Set CR25 when writing the UART2 Base Address. Serial Port 2 Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access UART2 registers. A[2:0] are decoded as XXXb. SMSC DS – SP37E760 DB5 DB4 DB3 ...

Page 56

... Set UART2 to 0FH i.e., set CR28.[3:0] = 1111b. This selects the share IRQ mechanism. Refer to Table 47, below. UART1 UART1 UART1 IRQ Output State OUT2 bit asserted 1 de-asserted asserted SMSC DS – SP37E760 DB5 DB4 DB3 ADR7 ADR6 ADR5 D3-D0 DMA SELECTED 0000 None 0001 DMA_A 0010 DMA_B 0011 DMA_C Table 46 - CR27: PP IRQ Selection Register D3-D0 ...

Page 57

... Bits D[3:0] of this register are used to select the DMA for the SCE. Bits D[7:4] are Reserved. Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ tristate. SMSC DS – SP37E760 UART2 UART2 ...

Page 58

... CR2F CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. The default value of this register after power up is 00H (Table 53). D7 CR2F R/W SMSC DS – SP37E760 Table 50 - CR2C: SCE DMA Select Register D3-D0 DMA SELECTED 0000 None ...

Page 59

... Schmitt Trigger Hysteresis I Input Buffer CLK Low Input Level High Input Level Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage High Input Leakage Input Current PWRGD SMSC DS – SP37E760 Table 54 – DC Electrical Characteristics SYMBOL MIN TYP MAX V 0.8 ILI V 2.0 IHI V ...

Page 60

... Output Leakage OD14 Type Buffer Low Output Level Output Leakage OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – SP37E760 SYMBOL MIN TYP MAX ...

Page 61

... CAPACITANCE T = 25° 1MHz PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance Table 56 - Capacitive Loading per Output Pin SIGNAL NAME SD[0:7] IOCHRDY IRQs DRQs TXD nRTS nDTR PD[7:0] nSLCTIN nINIT SMSC DS – SP37E760 SYMBOL MIN TYP MAX - ...

Page 62

... Data Access Time from nIOR Low t4 t5 Data to Float Delay from nIOR High t6 Parallel Port Setup t8 nIOR or nIOW Inactive for Transfers to and from ECP FIFO t9 nIOR Active to PINTR Inactive FIGURE 4 - MICROPROCESSOR READ TIMING SMSC DS – SP37E760 DATA VALID t8 t9 min 40 150 10 ...

Page 63

... Low t2 nIOW Width t3 A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High t4 t5 Data Hold Time from nIOW High nIOW Inactive to PINTR Inactive t7 FIGURE 5 - MICROPROCESSOR WRITE TIMING SMSC DS – SP37E760 DATA VALID t7 min typ max 40 150 10 ...

Page 64

... Clock High Time/Low Time for 32KHz t2 Clock Rise Time/Fall Time (not shown) t4 nRESET Low Time The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 24 x16MHz clock cycles. SMSC DS – SP37E760 min typ ...

Page 65

... IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx Inactive Delay from nIOW (Trailing Edge) t5 IRQx Inactive Delay from nIOW t6 IRQx Active Delay from nRIx SMSC DS – SP37E760 min 10 - FIGURE 7 SERIAL PORT TIMING Page 65 ...

Page 66

... PINTR Delay from nACK, nFAULT t3 PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK t4 nERROR Active to PINTR Active t5 PD0-PD7 Delay from nIOW Active t6 PINTR is the interrupt assigned to the Parallel Port SMSC DS – SP37E760 min 200 FIGURE 8 - PARALLEL PORT TIMING Page 66 t1 ...

Page 67

... Asserted to nWRITE Asserted NOTE: WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. FIGURE 9 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SMSC DS – SP37E760 t11 t16 t3 t4 t15 ...

Page 68

... SD<7:0> t8 IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> DATASTB ADDRSTB nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 10 - EPP 1.9 DATA OR ADDRESS READ CYCLE SMSC DS – SP37E760 t13 t18 t10 PData bus driven t5 by peripheral t28 t1 t14 t3 t15 t7 ...

Page 69

... NOTES WAIT is considered to have settled after it does not transition for a minimum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is inactive high true only FIGURE 11 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS SMSC DS – SP37E760 Parameter min ...

Page 70

... Command Deasserted to nWAIT Deasserted NOTES: 1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP W rite. 2. This number is only valid if WAIT is active when nIOW goes active. FIGURE 12 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SMSC DS – SP37E760 t6 t10 t20 t11 t13 ...

Page 71

... The timing is designed to allow operation at approximately 2.0Mbytes/sec over a 15ft cable shorter cable is used then the bandwidth will increase. 9.3.2.3 Forward-Idle When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low. SMSC DS – SP37E760 t15 t13 t3 t10 t5 ...

Page 72

... The timing for the dynamic driverchange is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July. 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. SMSC DS – SP37E760 Page 72 Rev. 04/13/2001 ...

Page 73

... Active to BUSY t5 BUSY Inactive to nSTROBE t6 BUSY Inactive to PDATE NOTE 1. The data is held until BUSY goes inactive or for time t3, whichever is applies if another data transfer is pending other data transfer is is held SMSC DS – SP37E760 Paramet min 600 600 450 680 ...

Page 74

... Asserted to nSTROBE Deasserted NOTES: 1. Maximum value only applies if there is data in the FIFO waiting to be written out. 2. BUSY is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 15 - ECP PARALLEL PORT FORWARD TIMING SMSC DS – SP37E760 ...

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... Maximum value only applies if there is room in the FIFO and a terminal count has not been received. ECP can stall by keeping nAUTOFD low. 2. nACK is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 16 - ECP PARALLEL PORT REVERSE TIMING SMSC DS – SP37E760 ...

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... PACKAGE OUTLINES - TE TE(2 ) SMSC DS – SP37E760 otes : 3.15 . rity (.00 4") max imu m. ...

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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter SMSC DS – SP37E760 D1/4 ...

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... SP37E760 REVISIONS PAGE(S) SECTION/FIGURE/ENTRY 1 Title SMSC DS – SP37E760 CORRECTION 3.3V Super I/O Controller for Embedded Applications changed to: 3.3V I/O Controller for Embedded Applications Page 78 DATE REVISED 04/13/01 Rev. 04/13/2001 ...

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