BT865AKRF Conexant Systems, Inc., BT865AKRF Datasheet

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BT865AKRF

Manufacturer Part Number
BT865AKRF
Description
Manufacturer
Conexant Systems, Inc.
Datasheet

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Company:
Connect Electronics Limited Connect Electronics Limited
Part Number:
BT865AKRF
Manufacturer:
CONEXANT
Quantity:
588
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Bt864A/Bt865A
YCrCb to NTSC/PAL Digital Video Encoder
Data Sheet
100138C
February 2003

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BT865AKRF Summary of contents

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Bt864A/Bt865A YCrCb to NTSC/PAL Digital Video Encoder Data Sheet 100138C February 2003 ...

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... Ordering Information Model Number Bt864AKRF YCrCb to NTSC/PAL Digital Video Encoder without Macrovision Bt865AKRF YCrCb to NTSC/PAL Digital Video Encoder with Macrovision Revision History Revision © 2003, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only ...

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Bt864A/Bt865A YCrCb to NTSC/PAL Digital Video Encoder Data Sheet The Bt864A/Bt865A is specifically designed for video systems requiring the generation of composite, Y/C (S-video) or RGB (SCART) video signals from 16-bit YCrCb digital video stream. Worldwide video ...

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Conexant 100138C 02/17/03 ...

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Contents Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 1-1. Bt864A/Bt865A Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...

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Tables Table 1-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...

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Circuit Description 1.1 Pin Descriptions Pin names, input/output assignments, numbers, and descriptions are listed in Table 1-1. details the block diagram. Table 1-1. Pin Assignments ( Pin Name I/O Pin # CLK I 43 RESET ...

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Circuit Description Table 1-1. Pin Assignments ( Pin Name I/O Pin # FIELD O 15 SLEEP I 39 SDA I/O 40 SCL I 41 VDD3V I 44 CVBS AGND (CVBS/B) 6 CVBS AGND (CVBS/G) ...

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Bt864A/Bt865A Data Sheet Figure 1-1. Bt864A/Bt865A Pinout Diagram FS ADJUST VBIAS VREF VAA COMP AGND AGND CVBS/B AGND CVBS/G AGND C/R Y/CVBS 100138C 02/17/ ...

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Circuit Description Figure 1-2. Detailed Block Diagram 1-4 Conexant Bt864A/Bt865A Data Sheet 100138_003 100138C 02/17/03 ...

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Bt864A/Bt865A Data Sheet 1.2 Clock TIming A clock signal with a frequency twice the pixel sampling rate must be present at the CLK pin. The device generates an internal pixel CLOCK that in slave mode is synchronized to the HSYNC* ...

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Circuit Description 1.4 HSYNC* Timing 1.4.1 Master Mode There are two HSYNC* timing modes in master mode; default mode and variable HSYNC* timing mode. The variable HSYNC* timing mode is enabled by setting ADJHSYNC high. This mode allows the user ...

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Bt864A/Bt865A Data Sheet Figure 1-3. HSYNC* Timing in Master Mode Reset ( Internal Pixel Clock/Counter Pixel Count Internal Horizontal Reset Default (2) HSYNC* (1) Horizontal Sync Pipeline Delay Analog Output Video Waveform GENERAL NOTE: Waveforms not to scale. ...

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Circuit Description 1.5 Video Timing The width of the analog horizontal sync pulses and the start and end of color burst are automatically calculated and inserted for each mode according to Color burst is disabled on appropriate scan lines. Serration ...

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Bt864A/Bt865A Data Sheet Figure 1-5. Interlaced 525-Line (PAL-M) Video Timing Analog FIELD 1 523 524 525 1 2 Analog FIELD 2 261 262 263 264 265 Analog FIELD 3 523 524 525 1 2 Analog FIELD 4 261 262 263 ...

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Circuit Description Figure 1-6. Interlaced 625-Line (PAL- Nc) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals Burst ...

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Bt864A/Bt865A Data Sheet Figure 1-7. Interlaced 625-Line (PAL- Nc) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals ...

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Circuit Description Figure 1-8. Interlaced 625-Line (PAL-N) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals Burst Phase = Reference Phase = ...

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Bt864A/Bt865A Data Sheet Figure 1-9. Interlaced 625-Line (PAL-N) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals Burst Phase = Reference Phase ...

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Circuit Description Figure 1-10. Noninterlaced 262-Line (NTSC) Video Timing 258 259 260 261 GENERAL NOTE: CCIR 624 line numbering convention. EVBI = 0. Figure 1-11. Noninterlaced 262-Line (PAL-M) Video Timing 258 259 260 261 262 1 GENERAL NOTE: CCIR 624 ...

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Bt864A/Bt865A Data Sheet 1.5.1 Reset If the RESET* pin is held low during a single rising edge of CLK, the subcarrier phase is set to zero, and the horizontal and vertical counters are held to the first pixel and second ...

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Circuit Description Table 1-3 lists the horizontal counter values for the end of horizontal sync, start of color burst, end of color burst, and the first active pixel for the various modes of operation. The front porch is the interval ...

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Bt864A/Bt865A Data Sheet 1.5.3 Master Mode Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal timing and from optional software bits. HSYNC* and VSYNC* are output following the rising edge of CLK. The HSYNC* output may be configured ...

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Circuit Description 1.5.5 FIELD Output The FIELD output indicates whether FIELD 1 (logical zero) or FIELD 2 (logical one) is being generated. This corresponds directly to the “bottom/top” convention of some MPEG decoders. Field transitions after the rising edge of ...

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Bt864A/Bt865A Data Sheet Figure 1-13. Three-Stage Chrominance Filter 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 0 Figure 1-14. Three-Stage Chrominance Filter (Passband) 0.5 0 –0.5 –1 –1.5 –2 –2.5 –3 0 0.2 100138C 02/17/ ...

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Circuit Description Figure 1-15. Luminance 2X Upsampling Filter Response 0 –10 –20 –30 –40 –50 –60 0 Figure 1-16. Luminance 2X Upsampling Filter Response (Passband) 0.5 0 –0.5 –1 –1.5 –2 –2.5 – ...

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Bt864A/Bt865A Data Sheet 1.5.10 Subcarrier Phasing In order to maintain correct SC-H phasing, the subcarrier phase is set to zero on the falling edge of HSYNC* associated with VSYNC* every four (NTSC) or eight (PAL) fields, unless the SCRESET bit ...

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Circuit Description 1.6 Power Saving Modes In SLEEP power-down mode (SLEEP pin set to 1), all analog and digital circuitry is disabled, and total device current consumption approaches 0 mA. Register states are preserved, but other chip functionality (including I ...

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Bt864A/Bt865A Data Sheet 1.7.2 DAC Coding For all video formats, the input luma and chroma values are scaled internally such that, after sync and setup (if enabled) are added, the output from sync to 100% white (for CVBS/Y outputs) is ...

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Circuit Description Figure 1-18. DAC Sinx/x Response (Passband) 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.8 –0.9 –1 0 1.8 Closed Captioning The Bt864A/Bt865A encodes NTSC/PAL–M closed captioning on scan line 21 and NTSC/PAL–M extended data services on scan ...

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Bt864A/Bt865A Data Sheet Closed-caption will override EVBI inserted data on lines 21 and 284 for 525-line formats, and lines 22 and 335 for 625-line formats. Closed-caption will be overridden by teletext if teletext is enabled on these lines. Closed caption ...

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Circuit Description Figure 1-19. Teletext Timing for Tb864A/Bt865A Encoder TTXREQ TTXDAT (6) CVBS CVBS/G Y/CVBS Internal Horizontal Reset Internal Clock (CLK) (9) Counter GENERAL NOTE: 1. TXE is enabled and video line is ...

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Bt864A/Bt865A Data Sheet 1.9.1 CCIR601 Operation (13.5 MHz pixel rate) The bit duration follows this pattern which repeats every 37 teletext bits. Each teletext data bit is carried by four CLKs except bits 10, 19, 28, and 37 which are ...

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Circuit Description 1.9.4 Teletext Clock Output The Bt864A/Bt865A can output the teletext clock from the TTXREQ pin by setting TXRM = 1. In this mode, this teletext clock would only be output on active teletext lines and each line would ...

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Bt864A/Bt865A Data Sheet 1.11 Anticopy Process (Bt865A Only) The anticopy process contained within the Bt865A is implemented according to the Macrovision version 7 specification developed by Macrovision Corporation in Sunnyvale, California. All luminance, chrominance, and composite video waveforms include the ...

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Circuit Description 1.15 Analog Outputs All digital-to-analog converters are designed to drive standard video levels into a combined RLOAD of 37.5 Ω. Unused outputs should be connected directly to ground to minimize supply switching currents. In standard mode, one S-Video ...

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Bt864A/Bt865A Data Sheet Figure 1-22. Y (Luminance) Video Output Waveform SETUPDIS = 26.68 1.000 100 IRE 9.07 0.340 7.5 IRE 7.60 0.285 40 IRE 0.00 0.000 Ω GENERAL NOTE: Typical with 37.5 load, nominal RSET. SMPTE 170 ...

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Circuit Description Figure 1-23. Y (Luminance) Video Output Waveform SETUPDIS = 26.68 1.000 8.0 0.300 0.00 0.000 GENERAL NOTE: Typical with 37.5 Ω load and nominal RSET. ITU-RBT.470-3 levels are assumed. 100% saturation (100/0/100/0) color bars are ...

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Bt864A/Bt865A Data Sheet Figure 1-24. C (Chrominance) Video Output Waveform SETUPDIS = 28.21 1.058 20.88 0.783 17.07 0.640 13.27 0.498 5.93 0.222 GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, and chroma on. SMPTE 170 M ...

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Circuit Description Figure 1-25. C (Chrominance) Video Output Waveform SETUPDIS = 28.88 1.083 21.08 0.791 17.07 0.640 13.07 0.490 5.27 0.198 GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, and chroma on. ITU-RBT.470-3 levels are assumed. ...

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Bt864A/Bt865A Data Sheet Figure 1-26. CVBS (Composite) Video Output Waveform SETUPDIS = 32.55 1.221 34 IRE 26.68 1.000 100 IRE 11.41 0.423 9.07 0.340 20 IRE 7.60 0.285 20 IRE 3.80 0.143 40 IRE 3.20 0.120 0.00 ...

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Circuit Description Figure 1-27. CVBS (Composite) Video Output Waveform SETUPDIS = 32.88 1.233 26.68 1.000 12.01 0.450 8.00 0.300 4.00 0.150 1.80 0.068 0.00 0.000 GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, and clipping off. ...

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Bt864A/Bt865A Data Sheet Table 1-14. RGB Output Table (RGBOUT = 1) SETUPDIS = 1 Description Iout (mA) White 18.68 Black 0 Blank 0 Iout typical with 37.5 Ω load, nominal RSET. GENERAL NOTE: FOOTNOTE: (1) BLANK occurs by external BLANK* ...

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Circuit Description 1-38 Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...

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Internal Registers A read-back bit map is given in Bit descriptions and detailed programming information follow the bit map. When a read does occur, only the data from start condition if pin ALTADDR is low and 0x89 if pin ...

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Internal Registers Table 2-2. Register Bit Map (1) Address EWSF2 EWSF1 A2 WSDAT[5:12] A4 WSDAT[13:20] (2) A6 SRESET Reserved (2) A8 Reserved (2) AA Reserved AC TXHS[7:0] AE TXHE[7:0] B0 LUMADLY[1:0] (2) B2 Reserved B4 TXBF1[7:0] B6 ...

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Bt864A/Bt865A Data Sheet 2.4 Programming Detail EWSF1 0 = Disable CGMS encoding in field Enable CGMS encoding in field 1 (line 20). EWSF2 0 = Disable CGMS encoding in field Enable CGMS encoding in ...

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Internal Registers CBSWAP 0 = Normal pixel sequence The Cb and Cr pixels can be swapped at the input of the pixel port. Refer to the pixel sequence section for more information. PORCH 0 = Front and back ...

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Bt864A/Bt865A Data Sheet NONINTL 0 = Interlaced operation Noninterlaced operation. SQUARE 0 = CCIR601 operation Square pixel operation. ESTATUS 0 = The I2C read-back information contains the version number The I2C read-back information contains ...

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Internal Registers 2-6 Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...

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PC Board Considerations A simplified schematic is shown in are listed in The layout should be optimized for lowest noise on the power and ground planes by providing good decoupling. The trace length between groups of VAA and GND ...

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PC Board Considerations Figure 3-1. Simplified Schematic VDD VAA C6 COMP C2 VBIAS C8 VREF C7 Bt864A/865A AGND GND RSET FSADJUST CVBS/G CVBS/B Y/CVBS C/R VAA To Filter LPF GND 22 pF 1.8 µH 270 pF 300 pF (1) FOOTNOTE: ...

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Bt864A/Bt865A Data Sheet Figure 3-2. Example Power Plane Layout 3.3 Decoupling 3.3.1 Device Decoupling For optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be ...

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PC Board Considerations 3.3.4 VREF Decoupling µ A 0.1 F ceramic capacitor should be used to decouple this pin to AGND. 3.3.5 VBIAS Decoupling µ A 0.1 F ceramic capacitor should be used to decouple this pin to AGND. 3.4 ...

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Bt864A/Bt865A Data Sheet 3.4.2 Analog Signal Interconnect The Bt864A/Bt865A should be located as close as possible to the output connectors to minimize noise pickup and reflections caused by impedance mismatch. The analog outputs are susceptible to crosstalk from digital lines; ...

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PC Board Considerations accuracy required by most industrial or consumer receivors. Note that a 30 ppm tolerance constraint applies for Teletext and MPEG2. Some applications call for maintaining correct Subcarrier-Horizontal (SC-H) phasing for correct color framing, which requires subcarrier coherence ...

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Bt864A/Bt865A Data Sheet 3.5.4 Reset Precautions The user should make the length of the traces connected to the RESET* input pin as short as possible. In addition, Conexant recommends that a 0.1 connected across the RESET* input pin and the ...

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PC Board Considerations inductor itself may induce 1% (0.1 dB) loss, and worst case subcarrier attenuation (including sinx/x loss) may be 7% with 10% tolerance reactive components. Any additional ferrites introduced for EMI control after termination should have less than ...

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Bt864A/Bt865A Data Sheet clock can generate significant energy at the aural carrier frequency. In the case of hard-edged, unblended characters having a font cell size which is a multiple of three pixels, harmonic energy at the aural carrier frequency may ...

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PC Board Considerations during the ninth clock pulse, then accept the data in subsequent bytes (autoincrementing the register address) until another stop condition is detected. Bit 8 of the address byte is the read/write bit (high = read from addressed ...

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Parametric Information 4.1 DC Electrical Parameters Table 4-1. Recommended Operating Conditions Parameter Symbol Power Supply (VAA and VDD) 3.3V Ambient Operating Temperature DAC Output Load Nominal RSET RSET Table 4-2. Absolute Maximum Ratings Parameter VAA and VDD (measured to ...

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Parametric Information Table 4-3. DC Characteristics (VDD = 5 V) Parameter Video D/A Resolution Output Current-DAC Code 1023 (Iout FS) Output Voltage-DAC Code 1023 Video Level Error (Nominal Resistors) Output Capacitance Digital Inputs (Except those specified below) Input High Voltage ...

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Bt864A/Bt865A Data Sheet 4.2 AC Electrical Parameters Table 4-4. AC Characteristics (VDD = 5 V, VAA = Parameter (3) Hue Accuracy (3) Color Amplitude Accuracy (4) Chroma AM/PM Noise (3) Differential Gain (3) Differential Phase ...

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Parametric Information Table 4-4. AC Characteristics (VDD = 5 V, VAA = Parameter Pipeline Delay Input Pixels to Composite Video Input Pixels to RGB Output VAA Supply Current VDD Supply Current 5.0 V 3.3 V ...

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Bt864A/Bt865A Data Sheet Figure 4-1. YCrCb Video Input and Output Timing CLK P[7:0], Y[7:0] 16-Bit Mode, BLANK*, HSYNC*, VSYNC* P[7:0] 8-Bit Mode, TTXDAT TTXREQ HSYNC*, VSYNC* FIELD (Output) CVBS/B, CVBS/G, Y/CVBS, C/R 100138C 02/17/ 2.4 .8 ...

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Parametric Information Figure 4-2. 52-Pin Metric Quad Flatpack (MQFP TOP VIEW SIDE VIEW DETAIL A 4 See Detail A BOTTOM VIEW All Dimensions in Dim. Min. A ---- A1 ...

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General Information: U.S. and Canada: (800) 854-8099 International: (949) 483-6996 Headquarters – Newport Beach 4311 Jamboree Rd. Newport Beach, CA. 92660-3007 ...

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