CY7C4281V-15JC Cypress Semiconductor Corporation., CY7C4281V-15JC Datasheet
CY7C4281V-15JC
Related parts for CY7C4281V-15JC
CY7C4281V-15JC Summary of contents
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... High-speed, low-power, first-in first-out (FIFO) memories • 16K x 9 (CY7C4261V) • 32K x 9 (CY7C4271V) • 64K x 9 (CY7C4281V) • 128K x 9 (CY7C4291V) • 0.35-micron CMOS for optimum speed/power • High-speed 100-MHz operation (10 ns read/write cycle times) • ...
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... Operating Range +125 C 0.5V to +3.6V Range Commercial 0. +0.5V CC Industrial 0. +0. CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 7C4261/71/81/91V-25 66 CY7C4281V CY7C4291V 64k x 9 128k x 9 32-pin PLCC 32-pin PLCC Ambient [1] Temperature +70 C 3.3V 300 +85 C 3.3V 300 mV ...
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... FIFO. PAF is synchronized to WCLK. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected HIGH, the FIFO’s outputs are in High Z (high-impedance) state. 3 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V ...
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... IH < Com’l 25 Ind Com’l 4 Ind Test Conditions MHz 3.3V CC [5, 6] 3.0V R2=510 GND 3 ns 4281V–4 2.0V /2 3.0V GND CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 7C4261/71/81/91V 7C4261/71/81/91V -15 -25 Min. Max. Min. Max. 2.4 2.4 0.4 0.4 2 0.5 0.8 0.5 0.8 10 +10 10 +10 10 + ...
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... Skew Time between Read Clock and SKEW2 Write Clock for Almost-Empty Flag and Almost-Full Flag Notes: 7. Pulse widths less than minimum values are not allowed. 8. Values guaranteed by design, not currently tested. CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 7C4261/71/81/91V 7C4261/71/81/91V -10 -15 Min. Max. Min. 100 2 ...
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... A VALID DATA t OE [10] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 6 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V NO OPERATION NO OPERATION t WFF 4281V–6 t REF t OHZ 4281V–7 ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers RSR RSS t t RSR RSS t t RSS RSR t RSF t RSF t RSF 7 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V [12 OE=0 4281V–8 ...
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... The first word is available the cycle after EF goes HIGH, always [14] t FRL t REF OLZ When t < minimum specification, t CLK SKEW2 SKEW1 8 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V [15 4281V–9 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 . ...
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... ENH ENS WEN1 t t ENS ENH WEN2 (if applicable) [14] t FRL RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V t DS DATA WRITE 2 t ENS t ENS t t REF REF ENH t ENH [14] t FRL t t REF SKEW2 DATA READ ...
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... SKEW1 D – WFF FF WEN1 WEN2 (if applicable) RCLK t t ENS REN1, REN2 LOW –Q DATA IN OUTPUT REGISTER DATA WRITE t WFF ENH A DATA READ 10 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V NO WRITE [9] DATA WRITE t SKEW1 t WFF t ENH t ENS t A NEXT DATA READ 4281V–11 ...
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... ENS ENH 20 Note PAF ENS ENH t ENS (m 1) words of the FIFO when PAF goes LOW. m words for CY7C4281V, and 128K , then PAF may not change state until the next WCLK. 11 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V WORDS Note18 IN FIFO t PAE t t ENS ENH 4281V– ...
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... RS is taken LOW. additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q even after additional reads occur. pins is written CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V PAF OFFSET PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET ...
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... Whether the flag offset registers are programmed as de- scribed in Table 1 or the default values are used, the programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V 16k Empty Offset (LSB) Reg ...
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... The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. 14 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V m), CY7C4271V (32k m), CY7C4281V CY7C4291V FF PAF [24] ...
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... Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4271V-10JC 15 CY7C4271V-15JC CY7C4271V-15JI 25 CY7C4271V-25JC 64kx9 Low Voltage Deep Sync FIFO Speed (ns) Ordering Code 10 CY7C4281V-10JC 15 CY7C4281V-15JC CY7C4281V-15JI 25 CY7C4281V-25JC RESET (RS) 9 CY7C4261V CY7C4271V CY7C4281V CY7C4291V Read Enable 2 (REN2) Configuration Package Package Name ...
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... J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier J65 32-Lead Plastic Leaded Chip Carrier 32-Lead Plastic Leaded Chip Carrier J65 CY7C4261V/CY7C4271V CY7C4281V/CY7C4291V Package Operating Type Range Commercial Commercial Industrial Commercial 51-85002-B ...