UPD70208HGF-10-3B9 Renesas Electronics Corporation., UPD70208HGF-10-3B9 Datasheet
UPD70208HGF-10-3B9
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UPD70208HGF-10-3B9 Summary of contents
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MICROPROCESSOR DESCRIPTION The PD70208H (V40HL high-speed, low-power 16-/8-bit microprocessor based on the PD70208 (V40 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions. The PD70216H (V50HL high-speed, low-power 16-bit microprocessor based on the PD70216 ...
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ORDERING INFORMATION (1) V40HL Part Number PD70208HGF-10-3B9 80-pin plastic QFP (14 (Resin thickness 2.7 mm) PD70208HGF-12-3B9 80-pin plastic QFP (14 (Resin thickness 2.7 mm) PD70208HGF-16-3B9 80-pin plastic QFP (14 (Resin thickness 2.7 mm) PD70208HGF-20-3B9 80-pin plastic QFP (14 (Resin thickness ...
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PIN CONFIGURATION (Top View) (1) V40HL • 80-pin Plastic QFP (14 20 mm) PD70208HGF-10-3B9 PD70208HGF-12-3B9 PD70208HGF-16-3B9 PD70208HGF-20-3B9 A16/PS0 NC A15 A14 A13 A12 A11 A10 GND GND 13 AD7 14 AD6 15 AD5 16 ...
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Plastic TQFP (Fine pitch) (12 PD70208HGK-10-9EU PD70208HGK-12-9EU PD70208HGK-16-9EU PD70208HGK-20-9EU A15 A14 3 A13 4 A12 ...
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Plastic QFJ (950 950 mil) PD70208HLP-10 PD70208HLP-12 PD70208HLP-16 PD70208HLP- A15 10 A14 11 A13 12 A12 13 A11 14 A10 GND 18 AD7 19 AD6 20 AD5 21 ...
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V50HL • 80-pin Plastic QFP (14 20 mm) PD70216HGF-10-3B9 PD70216HGF-12-3B9 PD70216HGF-16-3B9 PD70216HGF-20-3B9 A16/PS0 NC AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 GND NC GND AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NC NC END/ ...
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Plastic TQFP (Fine pitch) (12 PD70216HGK-10-9EU PD70216HGK-12-9EU PD70216HGK-16-9EU PD70216HGK-20-9EU AD15 AD14 3 AD13 4 AD12 ...
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Plastic QFJ (950 950 mil) PD70216HLP-10 PD70216HLP-12 PD70216HLP-16 PD70216HLP- AD15 10 AD14 11 AD13 12 AD12 13 AD11 14 AD10 15 AD9 16 AD8 17 GND 18 AD7 19 AD6 20 AD5 21 AD4 22 AD3 ...
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PIN NAMES A8-A15 : Address Bus A16/PS0-A19/PS3 : Address/Processor Status AD0-AD15 : Address Bus/Data Bus ASTB : Address Strobe BS0-BS2 : Bus Status BUFEN : Buffer Enable BUFR/W : Buffer Read/Write BUSLOCK : Bus Lock CLKOUT : Clock Output DMAAK0-DMAAK2 ...
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BLOCK DIAGRAM (1) V40HL TOUT2 TOUT1 TCU TCTL2 TCLK INTP7 INTP6 INTP5 ICU INTP4 INTP3 INTP2 INTP1 INTAK NMI CPU : Central Processing Unit CG : Clock Generator BIU : Bus Interface Unit BAU : Bus Arbitration ...
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V50HL TOUT2 TOUT1 TCU TCTL2 TCLK INTP7 INTP6 INTP5 ICU INTP4 INTP3 INTP2 INTP1 INTAK NMI SCU BIU WCU CPU BAU DMAU Data Sheet U13225EJ4V0DS00 PD70208H, 70216H POLL BUSLOCK BUFEN BUFR/W UBE ASTB IOWR IORD MWR ...
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DIFFERENCES FROM V40 AND V50 Item Operating supply voltage MAX. : 10, 12.5, 16, 20 MHz DD frequency MIN ...
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PIN FUNCTIONS ................................................................................................................................... 1.1 LIST OF PIN FUNCTIONS ........................................................................................................................... 1.2 PROCESSING OF UNUSED PINS .............................................................................................................. 2. MEMORY AND I/O CONFIGURATION ................................................................................................ 2.1 MEMORY SPACE ......................................................................................................................................... 2.2 I/O SPACE .................................................................................................................................................... 3. CPU ........................................................................................................................................................ 4. CG (CLOCK GENERATOR) ................................................................................................................. 5. BIU ...
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ELECTRICAL SPECIFICATIONS ......................................................................................................... 16 OPERATION .................................................................................................................................... 16 OPERATION .................................................................................................................................... 17. PACKAGE DRAWINGS ........................................................................................................................ 100 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................... 103 14 Data Sheet U13225EJ4V0DS00 PD70208H, 70216H ...
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PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS Pin Name Input/Output Note 1, 3 AD0 to AD15 3-state I/O Note 2, 3 AD0 to AD7 3-state I/O Note A15 3-state output Note 3 A16/PS0 to A19/PS3 ...
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Pin Name Input/Output DMAAK3/T D Output X DMARQ3 DMAAK0 to DMAAK2 Output DMARQ0 to DMARQ2 END/ GND IC 16 DMA acknowledge 3/serial transmit data Input DMA request 3/serial receive data DMA acknowledge Input DMA request I/O ...
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PROCESSING OF UNUSED PINS Table 1-1 shows the processing (recommended connection) of the unused pins. Use of a resistor with a resistance recommended to connect these pins to V Pin Name Input/Output Note ...
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Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive current higher than the latch invert current is necessary. (1) Output pin Output buffer Hi-Z control (2) ...
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MEMORY AND I/O CONFIGURATION 2.1 MEMORY SPACE The V40HL and V50HL can access a 1M-byte (512K-word) memory space. FFFFFH FFFFCH FFFFBH FFFF0H FFFEFH 00400H 003FFH 00000H Figure 2-2. Interface with Memory (1/2) A0-A19 D0-D7 Figure 2-1. Memory Map Reserved ...
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A1-A19 A0 UBE BSEL D0-D15 20 Figure 2-2. Interface with Memory (2/2) (b) V50HL Address Bus (19) 19 BSEL Memory Memory Upper Bank Lower Bank 512K Byte 512K Byte D8-D15 8 Data Bus (16) Data Sheet U13225EJ4V0DS00 PD70208H, 70216H 19 ...
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I/O SPACE In the V40HL and V50HL, I/ 64K bytes (32K words) can be accessed in an area independent of the memory. The various on-chip peripheral LSIs are set by accessing the system I/O area. Extended functions ...
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CPU The CPU has the same functions as the V20HL the use of the bus with on-chip peripherals, but in software terms the CPU is fully compatible. The internal block diagram of the CPU is shown in Figure 3-1. ...
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Figure 3-1. Internal Block Diagram of CPU (2/2) (b) V50HL Internal Address/Data Bus (20) ADM PS SS DS0 DS1 PFP DP TEMP ...
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CG (CLOCK GENERATOR) The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins, supplies it as the CPU operating clock and outputs ...
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BAU (BUS ARBITRATION UNIT) The BAU performs bus arbitration among bus masters. A list of bus masters (units which can acquire the bus) is shown below. Bus Master CPU DMAU REFU External bus master (HLDRQ pin input) The relative ...
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Bus Cycle Internal DMA Request Internal Refresh Request (Highest Priority) Bus Cycle HLDRQ Pin HLDAK Pin Internal Refresh Request (Highest Priority) Note The period in which the external bus master which has been given the bus after its release by ...
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WCU (WAIT CONTROL UNIT) The WCU has the function of automatically inserting a wait state (TW clock cycles in a CPU, DMAU or REFU bus cycle. 7.1 FEATURES • Automatic setting ...
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Figure 7-2. Example of I/O Space Division 64K-Byte I/O Area Remark The division specification and the size of each block are set by means of a system I/O area register. 7.2 RELATION BETWEEN WCU AND READY PIN When wait cycles ...
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REFU (REFRESH CONTROL UNIT) The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh interval can be set programmably. 8.1 FEATURES • Lowest-priority refreshing/highest-priority refreshing • 7-refresh queue • 16-bit refresh address • ...
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TCU (TIMER/COUNTER UNIT) The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally subset of the PD71054. 9.1 FEATURES • 3 16-bit counters • Six programmable count modes ...
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SCU (SERIAL CONTROL UNIT) The SCU performs control of serial communication (asynchronous). Its functions are a subset of the PD71051 excluding synchronous communication. Also, what was the control word register in the PD71051 has been divided into two: a ...
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ICU (INTERRUPT CONTROL UNIT) The ICU arbitrates among interrupt requests (maskable interrupts) generated inside and outside the V40HL and V50HL, and transfers one of them to the CPU. The ICU functions comprise the functions of the ...
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DMAU (DMA CONTROL UNIT) The DMAU has 4 DMA channels, and provides the functions (subset) of two LSIs, the PD71071 and PD71037. 12.1 FEATURES • Two operating modes ( PD71071 mode, PD71037 mode) • 20-bit address register • 16-bit ...
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STANDBY FUNCTIONS The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions. (1) HALT mode When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit) ...
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INSTRUCTION SET Identifier reg 8/16-bit general register (destination register in an instruction using two 8/16-bit general registers) reg’ Source register in an instruction using two 8/16-bit general registers reg8 8-bit general register (destination register in an instruction using two ...
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Identifier W Byte/word specification bit (0: byte, 1: word). However, when s =1, byte data of sign extension is 16-bit operand reg Register field (000 to 111) reg’ Register field (000 to 111) (source register in ...
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Table 15-3. Operand Description Legend Identifier AW Accumulator (16-bit) AH Accumulator (high-order byte) AL Accumulator (low-order byte) BW Register BW (16-bit) CW Register CW (16-bit) CL Register CL (low-order byte) DW Register DW (16-bit) BP Base pointer (16-bit) SP Stack ...
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Identifier (Blank mod 00 mem 000 001 010 011 100 IX 101 IY 110 DIRECT ADDRESS 111 BW Table 15-6. 8/16-Bit General Register Selection ...
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The instruction set is shown in tabular form on the following pages. Clock cycle shown in table is the time required for execution of instruction by the execution unit and is based on the following conditions. • Prefetch time and ...
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V50HL On the left of "/" : The value corresponding to byte processing ( word processing ( even address On the right of "/" : The value corresponding to word processing (W =1) of ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group MOV reg, reg’ mem, reg 1 0 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group REPC REPNC ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group INS reg8, reg8’ ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ADD reg, reg’ reg reg’ mem, reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ADD4S ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group MULU reg8 reg mem8 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group DIVU reg8 reg mem8 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group reg8 reg DIV mem8 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ADJBA ADJ4A ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group TEST reg, reg’ mem, reg 1 0 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group TEST1 reg8 reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group CLR1 reg8 reg ...
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Instruc- Operation Code Mnemonic Operand(s) tion Group SHL reg reg ...
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Instruc- Operation Code Mnemonic Operand(s) tion Group SHR reg reg ...
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Instruc- Operation Code Mnemonic tion Operand(s) Group SHRA reg reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ROL reg reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ROR reg reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group ROLC reg reg ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group RORC reg reg ...
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Instruc- Operation Code Mnemonic Operand(s) tion Group CALL near-proc regptr16 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group PUSH mem16 mod mem reg16 0 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group near-label short-label ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group short-label BNV short-label ...
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Instruc- Operation Code Mnemonic Operand(s) tion Group BRK imm8 ...
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Instruc- Operation Code tion Mnemonic Operand(s) Group HALT POLL ...
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ELECTRICAL SPECIFICATIONS Applied standard The electrical characteristics shown below are applied to devices other than the old models conforming to K mask. Therefore, these characteristics are different from those conforming to the K mask. For the electrical characteristics of ...
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DC CHARACTERISTICS (T = – 10% ( PD70208H, 70216H-10/12/16 Parameter Symbol Input voltage high V Input voltage low V Clock input voltage high V Clock input voltage low V Output ...
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AC CHARACTERISTICS (1) PD70208H, 70216H-10/12/ Parameter External clock input cycle External clock input high-level width (V =3 External clock input low-level width (V =1 External clock input rise time (1.5 3.0 V) External clock ...
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PD70208H, 70216H-10/12/ Parameter CLKOUT ASTB delay time ASTB high-level width ASTB address hold time Note 1 CLKOUT control 1 delay time Note 2 CLKOUT control 2 delay time Address float RD delay time CLKOUT RD delay time ...
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PD70208H, 70216H-10/12/ Parameter R D hold time (vs. SCU internal clock ) X CLKOUT SRDY delay time TOUT1 T D delay time X TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold ...
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PD70208H, 70216H- – Parameter External clock input cycle External clock input high-level width (V =3 External clock input low-level width (V =1 External clock input rise time (1.5 ...
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PD70208H, 70216H- – Parameter ASTB address hold time Note 1 CLKOUT control 1 delay time Note 2 CLKOUT control 2 delay time Address float RD delay time CLKOUT RD delay time CLKOUT ...
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PD70208H, 70216H- – Parameter TOUT1 TxD delay time TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold time (vs. CLKOUT ) TCTL2 hold time (vs. TCLK ) ...
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RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (T ( PD70208H, 70216H-20)) Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins other ...
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OPERATION OPERATING RANGE Masks PD70208H, 70216H-10/12/ 10% DD PD70208H, 70216H-20 ABSOLUTE MAXIMUM RATINGS (T A Parameter Symbol Supply voltage Input voltage Clock input voltage Output voltage Operating ambient ...
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DC CHARACTERISTICS (T = – Parameter Symbol Input voltage high V Input voltage low V Clock input voltage high V Clock input voltage low V Output voltage high V Output voltage low V Input leak ...
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AC CHARACTERISTICS (1) PD70208H, 70216H-10/12/ Parameter External clock input cycle External clock input high-level width (V =0 External clock input low-level width (V =0 External clock input rise time (0 ...
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PD70208H, 70216H-10/12/16 (T Parameter ASTB address hold time Note 1 CLKOUT control 1 delay time Note 2 CLKOUT control 2 delay time Address float RD delay time CLKOUT RD delay time CLKOUT RD delay time RD address delay time ...
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PD70208H, 70216H-10/12/ Parameter TOUT1 T D delay time X TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold time (vs. CLKOUT ) TCTL2 hold time (vs. TCLK ) TCTL2 high-level width TCTL2 ...
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PD70208H, 70216H- – Parameter External clock input cycle External clock input high-level width (V =0 External clock input low-level width (V =0 External clock input rise time (0.2 ...
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PD70208H, 70216H- – Parameter ASTB address hold time Note 1 CLKOUT control 1 delay time Note 2 CLKOUT control 2 delay time Address float RD delay time CLKOUT RD delay time CLKOUT ...
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PD70208H, 70216H- – Parameter TOUT1 TxD delay time TCTL2 setup time (vs. CLKOUT ) TCTL2 setup time (vs. TCLK ) TCTL2 hold time (vs. CLKOUT ) TCTL2 hold time (vs. TCLK ) ...
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RECOMMENDED OSCILLATOR The clock input circuits (1) and (2) shown below are recommended. (1) Ceramic resonator connection (T Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins other signal lines should ...
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AC Test Input Waveform (Except X1 and X2) ( operation) 2 Test Output Test Points ( operation) AC Test Input Waveform (Except X1 and X2) ( operation) 0 ...
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Clock Timing External Clock (Input) (X1) <11> CLKOUT (Output) Reset Timing CLKOUT (Output) <16> RESET (Input) RESOUT (Output) Ready Timing (1) T1 CLKOUT (Output) READY (Input) Variation Range Ready Timing (2) T1 CLKOUT (Output) <19> READY (Input) Variation Range Note ...
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Read Timing T4 CLKOUT (Output) 27 A16/PS0- A19/PS3 (Output) 27 A8-A15 (Output): V40HL UBE (Output): V50HL 27 AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL 33 ASTB (Output) BUFEN (Output) 38 BUFR/W (Output) MRD (Output) IORD (Output) BS0-BS2 (Output) 49 Note High-level ...
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Write Timing T4 CLKOUT (Output) 27> A16/PS0- A19/PS3 (Output) 27 A8-A15 (Output): V40HL UBE (Output): V50HL 27 AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL ASTB (Output) 33 BUFEN (Output) 38 BUFR/W (Output) MWR (Output) IOWR (Output) BS0-BS2 (Output) 49 Note High-level ...
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Status Timing T4 CLKOUT (Output) 27 A16/PS0- A19/PS3 (Output) 27 A8-A15 (Output): V40HL UBE (Output): V50HL 27 AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL 33 ASTB (Output) BS0-BS2 (Output) 49 Note 1 27 QS0, QS1 (Output) Notes 1. MRD, IORD, MWR, ...
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Interrupt Acknowledge Timing (V40HL) T1 CLKOUT (Output) A8-A15 (Output) <32> AD0-AD7 (I/O) ASTB (Output) <38> INTAK (Output) BUFEN (Output) BUFR/W (Output) BUSLOCK (Output) Notes 1. Slave address in case of interrupt from external PD71059. Invalid data in case of interrupt ...
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Interrupt Acknowledge Timing (V50HL) T1 CLKOUT (Output) <32> AD0-AD15 (I/O) ASTB (Output) <38> INTAK (Output) <38> BUFEN (Output) BUFR/W (Output) BUSLOCK (Output) Notes 1. Slave address in case of interrupt from external PD71059. Invalid data in case of interrupt from ...
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HLDRQ/HLDAK Timing (1) CLKOUT (Output) <51> HLDRQ (Input) HLDAK (Output) Note BS0-BS2 (Output) Note A16/PS0 to A19/PS3, UBE, BUFEN, BUFR/W, MRD, IORD, MWR, IOWR (all output): V40HL, V50HL A8-A15 (output): V40HL AD0-AD7 (input/output): V40HL AD0-AD15 (input/output) V50HL Remark A dashed ...
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POLL, NMI Input Timing CLKOUT (Output) POLL (Input) NMI (Input) BUSLOCK Output Timing CLKOUT (Output) <27> BUSLOCK (Output) Access Interval MRD (Output) IORD (Output) MWR (Output) IOWR (Output <24> <23> <86> <86> <86> <86> Data Sheet U13225EJ4V0DS00 PD70208H, ...
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Refresh Timing (V40HL) T4 CLKOUT (Output) 27 A16/PS0- A19/PS3 (Output) 27 A8-A15 (Output) 27 AD0-AD7 (I/O) 33 ASTB (Output) BUFEN (Output) MRD (Output) REFRQ (Output) 49 BS0-BS2 (Output) Remark A dashed line indicates high impedance ...
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Refresh Timing (V50HL) T4 CLKOUT (Output) 27 A16/PS0- A19/PS3 (Output) 27 UBE (Output) 27 AD0-AD15 (I/O) 33 ASTB (Output) BUFEN (Output) MRD (Output) REFRQ (Output) 49 BS0-BS2 (Output) Remark A dashed line indicates high impedance ...
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TCU Timing (1) CLKOUT (Output) <72> TCTL2 (Input) TOUTn (Output) (n=1, 2) Note Applies to TOUT2 output. TCU Timing (2) <82> <81> TCLK (Input) TCTL2 (Input) TOUTn (Output) (n=1, 2) Note Applies to TOUT2 output. <74> <77> <76> Note <80> ...
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SCU Timing RxD (Input) TOUT1 (Output) TxD (Output) CLKOUT (Output) SRDY (Output) 96 <68> <69> 16 Cycles or 64 Cycles 16 Cycles or 64 Cycles <71> <70> Data Sheet U13225EJ4V0DS00 PD70208H, 70216H ...
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DMAU Timing (1) T4 CLKOUT (Output) 49 BS0-BS2 (Output) 33 ASTB (Output) 27 A16/PS0- A19/PS3 (Output) 27 A8-A15 (Output): V40HL UBE (Output): V50HL 27 AD0-AD7 (I/O): V40HL AD0-AD15 (I/O): V50HL DMAAK (Output) MRD (Output) IORD (Output) MWR (Output) IOWR (Output) ...
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DMAU Timing (2) T1 CLKOUT (Output) TC (Input/Output) END (Input/Output) CLKOUT (Output) DMARQn (Input) (n=0- <60> <64> <62> <65> <66> Data Sheet U13225EJ4V0DS00 PD70208H, 70216H T4 <61> <63> ...
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DMAU Timing (3) (Cascade Mode) In Normal Operation: CLKOUT (Output) DMARQ (Input) DMAAK (Output) When Refresh Cycle is Inserted: CLKOUT (Output) DMARQ (Input) DMAAK (Output) ICU Timing INTPn (Input) (n=1-7) T1 <66> <66> <54> <54> <67> Data Sheet U13225EJ4V0DS00 PD70208H, ...
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PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x20 NOTE 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ...
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PIN PLASTIC TQFP (FINE PITCH NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC QFJ (950 x 950 mil NOTES 1. Controlling dimension 2. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 102 ...
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RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For the details of recommended soldering conditions for the surface mounting type, refer to the information document Semiconductor Device Mounting Technology ...
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L, F masks Soldering Method Infrared reflow Package peak temperature: 235 C, Time: 30 sec. max. (210 ˚C min.), Number of times: 3 max. VPS Package peak temperature: 215 C, Time: 40 sec. (200 C min.) Number of times: ...
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PD70208HGK- -9EU : 80-pin plastic TQFP (fine pitch) (12 PD70216HGK- -9EU : 80-pin plastic TQFP (fine pitch) (12 ( masks Soldering Method Infrared reflow Package peak temperature : 230 C, Time: 30 sec. max. (210 C ...
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PD70208HLP- : 68-pin plastic QFJ (950 PD70216HLP- : 68-pin plastic QFJ (950 ( masks Soldering Method Infrared reflow Package peak temperature : 230 C, Time: 30 sec. max. (210 C min.), Number of timers: 1, Number ...
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Data Sheet U13225EJ4V0DS00 PD70208H, 70216H 107 ...
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PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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V20, V20HL, V30, V30HL, V40, V40HL, V50, V50HL and V series are trademarks of NEC Corporation. The information in this document is current as of January, 1999. The information is subject to change without notice. For actual design-in, refer ...