DS1397 Dallas Semiconductor, DS1397 Datasheet

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DS1397

Manufacturer Part Number
DS1397
Description
RAMified real time clock
Manufacturer
Dallas Semiconductor
Datasheet

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Part Number:
DS1397
Manufacturer:
DALLAS
Quantity:
400
Part Number:
DS1397
Manufacturer:
DALLAS
Quantity:
400
Part Number:
DS1397
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FEATURES
ORDERING INFORMATION
DS1395
DS1395S
DS1397
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor databooks.
Ideal for EISA bus PCs
Functionally compatible with MC146818 in 32 KHz
mode
Totally nonvolatile with over 10 years of operation in
the absence of power
Self-contained subsystem includes lithium, quartz,
and support circuitry
Counts seconds, minutes, hours, day of the week,
date, month, and year with leap year compensation
Binary or BCD representations of time, calendar, and
alarm
12- or 24-hour clock with AM and PM in 12-hour mode
Daylight Savings Time option
Interfaced with software as 64 register/RAM locations
plus 4K x 8 of static RAM
Programmable square wave output signal
Bus-compatible interrupt signals (IRQ)
Three interrupts are separately software-maskable
and testable:
28-pin JEDEC footprint
Available as chip (DS1395/DS1395S) or stand alone
module with embedded lithium battery and crystal
(DS1397)
Copyright 1995 by Dallas Semiconductor Corporation.
– 14 bytes of clock and control registers
– 50 bytes of general and control registers
– Separate 4K x 8 nonvolatile SRAM
– Time-of-day alarm once/second to once/day
– Periodic rates from 122 s to 500 ms
– End-of-clock update cycle
RTC Chip; 28–pin DIP
RTC Chip; 28–pin SOIC
RTC Module; 28–pin DIP
PIN ASSIGNMENT
RAMified Real Time Clock
DS1397 28-Pin Encapsulated Package (720 mil)
STBY
V
STBY
STBY
A0
A1
X2
X1
D0
D1
D2
D3
D4
D5
D6
D7
SS
DS1395S 28-Pin SOIC (330 mil)
V
V
DS1395 28-Pin DIP (600 mil)
NC
NC
SS
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
SS
A0
A1
X2
X1
D0
D1
D2
D3
D4
D5
D6
D7
1
2
10
3
4
5
6
7
8
9
11
12
13
14
4
10
11
14
1
2
3
5
6
7
8
9
12
13
10
13
11
12
14
1
2
3
4
5
6
7
8
9
DS1395/DS1397
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
21
20
19
18
17
16
15
22
A2
A3
V
SQW
A4
A5
V
B GND
IRQ
RESET
RD
WR
XRAM
RTC
A2
A3
V
SQW
A4
A5
NC
NC
WR
XRAM
DD
BAT
IRQ
RESET
RD
RTC
DD
A2
A3
V
SQW
A4
A5
V
IRQ
RESET
RD
B GND
WR
XRAM
RTC
BAT
DD
DS1395/DS1397
020794 1/19

Related parts for DS1397

DS1397 Summary of contents

Page 1

... DS1395 28-Pin DIP (600 mil SQW STBY IRQ RESET XRAM RTC DS1397 28-Pin Encapsulated Package (720 mil) 020794 1/19 ...

Page 2

... DS1395/DS1397 PIN DESCRIPTIONS V V – Bus operational power is supplied to the part DD, SS via these pins. The voltage level present on these pins should be monitored to transition between operational power and battery power. D0-D7 – Data Bus (bidirectional): Data is written into the device from the data bus if either XRAM or RTC is asserted during a write cycle at the rising edge pulse ...

Page 3

... module is switched over to an internal power source in L the case of the DS1397 external battery con- nected to the V and BGND pins in the case of the BAT DS1395 and DS1395S, so that power is not interrupted to timekeeping and nonvolatile RAM functions. ...

Page 4

... DS1395/DS1397 TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by read- ing the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format ...

Page 5

... DS139X BLOCK DIAGRAM Figure 1 DS1395/DS1397 DECODER REGISTER INDEX 020794 5/19 ...

Page 6

... DS1395/DS1397 REAL TIME CLOCK RAM MAP Figure 2 RTC INDIRECT ADDRESS REGISTER RTC +1 RTC DATA REGISTER INDIRECT ADDRESS 00 14–BYTES RTC 13 14 50–BYTES USER RAM 63 EXTENDED RAM ADDRESS MAP Figure 3 XRAM THRU XRAM + 1F XRAM + 20 XRAM + 21 THRU XRAM + 3F 020794 6/ ...

Page 7

... Year USER NONVOLATILE RAM - RTC The 50 user nonvolatile RAM bytes are not dedicated to any special function within the DS1395/DS1397. They can be used by the application program as nonvolatile memory and are fully available during the update cycle. This memory is directly accessible in the RTC section. ...

Page 8

... DS1395/DS1397. The act of reading Register C clears all active flag bits and the IRQF bit. OSCILLATOR CONTROL BITS When the DS1395/DS1397 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium battery from being used until it is installed in a system ...

Page 9

... UPDATE CYCLE The DS1395/DS1397 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to one, the user copy of the double buffered time, calendar, and alarm bytes is frozen and will not update as the time incre- ments ...

Page 10

... When the AIE bit is set to zero, the AF bit does not initiate the IRQ signal. The internal functions of the DS1395/DS1397 do not affect the AIE bit but is cleared by RESET. UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write bit that enables the Update Ended Flag (UF) bit in Register C to assert IRQ ...

Page 11

... RTC data and RAM data are question- able. BIT 6 THROUGH BIT 0 - The remaining bits of Register D are reserved and not usable. They cannot be written and, when read, they will always read zero. DS1395/DS1397 LSB BIT 2 BIT 1 BIT 0 0 ...

Page 12

... Oscillator Startup From Software Enable Via DV Bits IRQ Release from RD High IRQ Release from RESET Low 020794 12/19 -0.3V to +7.0V V – 500 mW DS1397: – +70 C DS1395: – +125 260 C for 10 seconds SYM MIN MAX V 4 ...

Page 13

... IRQ RELEASE DELAY RD V HIGH RESET V HIGH IRQ t IRDS OSCILLATOR START-UP SQW Pin WR V DV0–2 NOTE: Timing assumes RS3-0 Bits = 0011, minimum t t RWL t IRR t RC HIGH . PI DS1395/DS1397 020794 13/19 ...

Page 14

... DS1395/DS1397 BUS TIMING PARAMETER SYM Cycle Time t CYC Pulse Width, RD/WR Low PW RWL Signal Rise and Fall Time, RTC XRAM, RD, WR Address Hold Time t AH Address Setup Time Before RD t ARS Address Setup Time Before WR t AWS RTC/XRAM Select Setup Time ...

Page 15

... CE is chip enabled for access, an internal signal which is defined by (RD + WR) (XRAM + RTC). t CYC VALID RWL t t DSW VALID VALID t DDR RWL t DHR MIN TYP MAX 0 150 300 < 4. >4.0V 10 DS1395/DS1397 AH t DHW UNITS NOTES years 020794 15/19 ...

Page 16

... Clock Accuracy for (DS1397 only) Clock Accuracy Temperature Co- K efficient (DS1397) Clock Temperature Coefficient t O Turnover Temperature (DS1397 only) Chip Enable Threshold (DS1397 CE THR only) POWER–UP CONDITION CE 4.5V 4.25V 4. POWER FAIL NOTE internal signal generated by the power switching reference in the DS139X products. ...

Page 17

... V t BAT t FB PKG DIM IN. MM DS1395/DS1397 DR 28–PIN MIN MAX 1.445 1.470 36.70 37.34 0.530 0.550 13.46 13.97 0.140 0.160 3.56 4.06 0.600 0.625 15.24 15.88 0.015 0.040 0.38 1.02 0.120 0.145 3.05 3.68 0.090 0.110 2.29 2 ...

Page 18

... DS1395/DS1397 DS1395S 28–PIN SOIC 0–8 deg. typ 020794 18/19 PKG 28-PIN DIM MIN MAX A IN. 0.706 0.728 MM 17.93 18.49 B IN. 0.338 0.350 MM 8.58 8.89 C IN. 0.086 0.110 MM 2.18 2.79 D IN. 0.020 0.050 MM 0.58 1.27 E IN. 0.002 0.014 MM 0.05 0.36 F IN. 0.090 0.124 MM 2.29 3.15 0.050 BSC G IN IN. 0.460 ...

Page 19

... DS1397 28–PIN 720 MIL FLUSH ENCAPSULATED EQUAL SPACES AT .100 .010 TNA PKG DIM MIN A IN. 1.520 MM 38.61 B IN. 0.695 MM 17. IN. 0.350 MM 8.89 D IN. 0.100 MM 2.54 E IN. 0.015 MM 0.38 F IN. 0.110 MM 2. IN. 0.090 MM 2.29 H IN. 0.590 F MM 14. IN. 0.008 MM 0.20 K IN. ...

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