FDC37C932APM Standard Microsystems, FDC37C932APM Datasheet
FDC37C932APM
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FDC37C932APM Summary of contents
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Plug and Play Compatible Ultra I/O™ Controller with Soft Power Management 5 Volt Operation ISA Plug-and-Play Standard (Version 1.0a) Compatible Register Set Soft Power Management, SMI Support ACPI/Legacy Support - SCI/SMI Support - Power Management Timer - Power Button Override ...
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FEATURES ........................................................................................................................................1 GENERAL DESCRIPTION..................................................................................................................4 PIN CONFIGURATION.......................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS...........................................................................................6 FUNCTIONAL DESCRIPTION ..........................................................................................................15 SUPER I/O REGISTERS ...........................................................................................................15 HOST PROCESSOR INTERFACE.............................................................................................15 FLOPPY DISK CONTROLLER...................................................................................................16 FDC INTERNAL REGISTERS....................................................................................................16 INSTRUCTION SET .........................................................................................................................44 SERIAL PORT (UART) .....................................................................................................................70 INFRARED INTERFACE...................................................................................................................85 PARALLEL PORT.............................................................................................................................86 IBM XT/AT COMPATIBLE, ...
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IRQ Options - Two High Speed NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Programmable Baud Rate Generator - Modem Control Circuitry Including 230K and 460K Baud - IrDA, HP-SIR, ASK-IR Support IDE Interface - Relocatable to ...
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... The PCC software and register compatible with SMSC's proprietary 82077AA core. IBM, PC/XT and PC/AT are registered trademarks and PS trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and Multi-Mode are trademarks of Standard Microsystems Corporation 4 '95. Through internal registers, ...
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GND 1 DRVDEN0 2 DRVDEN1 3 nMTR0 4 nDS1 5 nDS0 6 nMTR1 7 GND 8 nDIR 9 nSTEP 10 nWDATA 11 nWGATE 12 nHDSEL 13 nINDEX 14 nTRK0 15 nWRTPRT 16 FDC37C93xAPM nRDATA 17 nDSKCHG 18 MEDIA_ID1 19 mEDIA_ID0 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. PROCESSOR/HOST INTERFACE 72:79 System Data Bus 41:52 System Address Bus 53 Chip Select/SA12 (Active Low)(Note Address Enable (DMA master has bus control) 90 I/O Channel Ready 80 Reset Drive 67:61, Interrupt ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. 12 Write Gate 11 Write Disk Data 13 Head Select (1 = side 0) 9 Step Direction (1 = out) 10 Step Pulse 18 Disk Change 5,6 Drive Select Lines 7,4 Motor On Lines ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. 154 Data Carrier Detect 2 (Note 4) 153 Ring Indicator 2 (Note 4) 23 IDE1 Enable (Note 4) 24 IDE1 Chip Select 0 (Note 4) 25 IDE1 Chip Select 1 (Note 4) 30 IOR ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. 92 Keyboard Clock 93 Mouse Data 94 Mouse Clock SOFT POWER MANAGEMENT INTERFACE 33 Power On (Note 4) 34 Button Input (Note 4) 96 GPI/O; IRQ In (Note 4) 97 GPI/O; IRQ In/IRQ 13 ...
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SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15. Note 2: nYY - ...
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Description of Multifunction Pins with GPI/O and Other Alternate Functions Pin Original Alternate No. Function Function 1 Function 2 19 MEDIA_ID1 GPI/O 20 MEDIA_ID0 GPI/O 23 nIDE1_OE GPI/O 24 nHDCS0 GPI/O 25 nHDCS1 GPI/O 26 IDE1_IRQ GPI/O 30 nIOROP GPI/O ...
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Pin Original Alternate No. Function Function 1 Function 2 27 nHDCS2 SA13 28 nHDCS3 SA14 29 IDE2_IRQ SA15 53 nCS/ GPI/O IRQ in 97 GPI/O IRQ in WDT 98 GPI/O Timer Output/ IRRX Power LED 99 GPI/O ...
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BUFFER TYPE DESCRIPTIONS BUFFER TYPE DESCRIPTION I Input, TTL compatible. IS Input with Schmitt trigger. I/OD16P Input/Output, 16mA sink, 90uA pull-up. I/O24 Input/Output, 24mA sink, 12mA source. I/O4 Input/Output, 4mA sink, 2mA source. O4 Output, 4mA sink, 2mA source. O8SR ...
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IRQ13* nPowerOn SOFT POWER SMI Button_In POWER MANAGEMENT ACPI/SCI MANAGEMENT VTR AB_DATA* ACCESS.bus AB_CLK* ADDRESS BUS DATAIN* SERIAL DATAOUT* EEPROM CLK*, ENABLE* nIOR nIOW AEN SA[0:12] (nCS) SA[13-15] HOST CPU SD[O:7] PROPRIETARY INTERFACE COMPATIBLE DRQ[0:3] FLOPPYDISK nDACK[0:3] CONTROLLER TC ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports, Bank 2 of ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the direction of ...
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PS/2 Model 30 Mode 7 INT PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates direction; a logic "1" indicates outward direction. BIT 1 WRITE PROTECT Active high status ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 Active high status of ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface 7 6 MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These two bits are ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC does not characteristics modified for tape support. The contents of this register are not used internal ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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Table 9 - Drive Type ID DIGITAL OUTPUT REGISTER Bit 1 Bit Note: L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. REGISTER 3F3 - DRIVE TYPE ID Bit 5 ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 ...
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Table 13 - Default Precompensation Delays PRECOMPENSATION DATA RATE DELAYS 2 Mbps* 20 Mbps 41.67 ns 500 Kbps 125 ns 300 Kbps 125 ns 250 Kbps 125 ns *The 2Mbps data rate is only available ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register 7 6 RQM DIO NON DMA BIT 0-3 DRVx BUSY These bits are ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC/AT Mode 7 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs D0-6 will remain in a high impedance ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 11 ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check ...
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Table 16 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 17 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC, a ...
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PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care" (FINTR and DRQ are always valid), TC and DENSEL become active low. ...
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Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is ...
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DMA Mode - Transfers from the Host to the FIFO The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 19 - Description of Command Symbols SYMBOL NAME EOT End of Track GAP GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload Time LOCK MFM MFM/FM Mode Selector MT Multi-Track Selector DESCRIPTION The final sector ...
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Table 19 - Description of Command Symbols SYMBOL NAME N Sector Size Code NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative ...
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Table 19 - Description of Command Symbols SYMBOL NAME SC Number of Sectors Per Track SK Skip Flag SRT Step Rate Interval The time interval between step pulses issued by the FDC ST0 Status 0 ST1 Status 1 ST2 Status ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 20 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 -------- ST0 ...
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PHASE R/W D7 Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT is ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 24 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 27 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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During the command phase of the seek or recalibrate operation, the FDC is in the BUSY state, but during the execution phase the NON-BUSY state. At this time, another Seek or Recalibrate command may be issued, and ...
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Sense Drive Status Sense Drive Status obtains information. It has no execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the drive status information. Specify The Specify command sets the initial values ...
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Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", ...
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Relative Seek command is 255 (D). The internal register, PCN, will overflow as the cylinder number crosses track 255 and will contain 39 (D). The resulting PCN value is thus (RCN + PCN) mod 256. Functionally, the ...
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On the read back by the FDC, the controller must begin synchronization at the beginning of the sync field. For the conventional mode, the internal PLL VCO is enabled approximately 24 bytes from the start of the Gap2 field. But, ...
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Table 30 - Effects of WGATE and GAP Bits WGATE GAP LOCK In order to protect systems with long DMA latencies against older application software that can disable the FIFO, the LOCK ...
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The FDC37C93xAPM incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTS perform serial-to- parallel conversion on received characters and parallel-to-serial conversion characters. The data rates are independently programmable from ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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BIT 1 Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. BIT 2 Setting this bit to ...
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Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT BIT BIT BIT PRIORITY LEVEL Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: BIT 0 and 1 These two bits specify the number of bits in each ...
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This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. BIT 0 This bit controls the Data Terminal Ready (nDTR) output. When ...
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Line Status Register is read. BIT 2 Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by ...
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MODEM STATUS REGISTER (MSR) Address Offset = 6H, DLAB READ/WRITE This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to this current state information, four bits of the MODEM ...
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The input clock to the BRG is a 1.8462 MHz clock. Table 33 shows the baud rates possible with a 1.8462 MHz crystal. Effect Of The Reset on Register File The Reset Function Table (Table ...
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Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt. FIFO POLLED MODE OPERATION With FCR ...
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Table 33 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432 MHz Clock for 115.2k ; Using 3.6864 MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK ...
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Table 34 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift Keyed IR. transmission can use the standard ...
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The FDC37C93xAPM incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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Table 36 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 2 (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the ...
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IBM XT/AT COMPATIBLE, BI- DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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EPP DATA PORT 1 ADDRESS OFFSET = 05H The EPP Data Port 1 is located at an offset of '05H' from the base address. DATA PORT 0 for a description of operation. This register is only available in EPP mode. ...
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Write Sequence of Operation 1. The host selects an EPP register, places data on the SData bus and drives nIOW active. 2. The chip drives IOCHRDY inactive (low WAIT is not asserted, the chip must wait until WAIT ...
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EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi- directional modes are also available EPP Read, Write or Address cycle is currently executing, then the PDx bus is in ...
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The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. 7. When the host deasserts nIOR the chip deasserts nDATASTB or nADDRSTRB. 8. Peripheral tri-states the PData bus. 9. ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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D7 D6 data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 0 0 cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB compress intrValue ecr MODE Note 1: These registers are available in all modes. Note 2: All FIFOs use one common ...
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Table 38 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition Table 39 - ECP Register Definitions NAME ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU due to a low to high transition on ...
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Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h are written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the ...
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BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least one free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The ...
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Table 41A - Extended Control Register R/W 000: Standard Parallel Port Mode. In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt ...
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DMA TRANSFERS DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed I/O ...
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The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold equivalent to a threshold of ...
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PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. ...
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CONNECTOR PIN # CHIP PIN # SPP MODE 1 144 2 138 3 137 4 136 5 135 6 134 7 133 8 132 9 131 10 129 11 128 12 127 13 126 14 143 15 142 nERROR 16 ...
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AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. FDC Power Management ...
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Register Behavior Table 44 reiterates the AT and PS/2 (including Model 30) configuration registers available. It also shows the type of access permitted. order to maintain software transparency, access to all the registers must be maintained. As Table 44 shows, ...
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Table 44 - PC/AT and PS/2 Available Registers Available Registers Base + Address PC-AT Access to these registers DOES NOT wake up the part 00H ---- 01H ---- 02H DOR (1) 03H --- 04H DSR (1) 06H --- 07H DIR ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 46 - State of Floppy Disk Drive Interface Pins in Powerdown FDD PINS RDATA ...
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UART Power Management Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23- B4 and B5. When set, these bits allow the following auto power management operations: 1. The transmitter ...
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INTEGRATED DRIVE ELECTRONICS INTERFACE The FDC37C93xAPM contains interfaces. This enables hard embedded controllers (AT or IDE interfaced to the host processor. interface performs the address decoding for the IDE interface, generates the buffer enables for external buffers and ...
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IDE OUTPUT ENABLES Two IDE output Enables are available. The IDE output enables treat all IDE transfers as 16 bit transfers. Option 1 Option 2 Note 1: The low and high byte transfers for IDE1 goes through external buffers controlled ...
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The FDC37C93xAPM contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used, then nROMCS and nROMDIR must be tied high so as not to interfere with the boot ROM. nROMCS ...
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SD[15:8] FDC37C93xAPM SD[7:0] IDE1_OE B1 IDE2_OE FIGURE 3 - IDE OUTPUT ENABLE OPTION 2 IDE Channel 1 BIOS NC IDE Channel 2 119 Option 2 ...
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RD Bus Functionality The following four cases described below illustrate the use of the RD Bus. Case 1: nROMCS and nROMOE as original function. The RD bus can be used as the RD bus or one or more RD pins ...
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GENERAL PURPOSE I/O FUNCTIONAL DESCRIPTION The FDC37C93xAPM provides a set of flexible Input/Output control functions to the system designer through a set of General Purpose I/O pins (GPI/O). These GPI/O pins may perform simple I/O or may be individually configured ...
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The FDC37C93xAPM also has 28 GPI/O ports that are the first alternate functions of pins Table 47B - Multifunction GPI/O Pins PIN ORIGINAL ALTERNATE NUMBER FUNCTION FUNCTION 1 19 MEDIA_ID1 20 MEDIA_ID0 23 nIDE1_OE 24 nHDCS0 25 nHDCS1 26 IDE1_IRQ ...
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PIN ORIGINAL ALTERNATE NUMBER FUNCTION FUNCTION 1 157 nDSR2 (2) 158 nRTS2 (2) (3) 159 nCTS2 (2) 160 nDTR2 (2) (3) Note 1: At power-up, RD0-RD7, nROMCS and nROMOE function as the XD Bus. To use RD0- RD7 for functions ...
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Table 48A - Index and Data Register REGISTER ADDRESS Index 0xE0, E2, E4, EA Data Index address + 1 Table 48B - Index and Data Register Normal (Run) Mode INDEX 0x01 Access to GP1 (L8 - CRF6) 0x02 Access to ...
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GPI/O ports contain alternate functions which are either output-type or input-type. The GPI/O SD-bit D-TYPE nIOW Transparent nIOR GPI/O GPIO Register Configuration Bit-n Register bit-3 (Alt Function) Alternate Input Function FIGURE 4 - GPI/O HAVING AN INPUT-TYPE ALTERNATE FUNCTION [GP10, ...
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Alternate Output Function SD-bit D-TYPE nIOW 0 Transparent 1 nIOR GPI/O Register Bit-n FIGURE 5 - GPI/O HAVING AN OUTPUT-TYPE ALTERNATE FUNCTION [GP12 - GP17, GP20, GPIO GPI/O Configuration Configuration Register bit-3 Register bit-1 (Alt Function) (Polarity ...
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General Purpose I/O Configuration Registers Assigned to each GPI/O port is an 8-bit GPI/O Configuration Register which independently program each I/O port. GPI/O Configuration Registers accessible when the FDC37C93xAPM is in the Configuration Mode; more information can be found in ...
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Table 49 - GPI/O Configuration Register Bits [3:0] ALT FUNC POLARITY BIT 3 INT EN 0= BIT 2 DISABLE NO INVERT 0=DISABLE 1=SELECT 1=INVERT 1=ENABLE BIT 1 I/O 0= BIT ...
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Table 49 - GPI/O Configuration Register Bits [3:0] ALT FUNC POLARITY BIT 3 INT EN 0= BIT 2 DISABLE NO INVERT 0=DISABLE 1=SELECT 1=INVERT 1=ENABLE The alternate function of GP10 and GP11 allows these GPI/O port ...
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Reading and Writing GPI/O Ports When a GPI/O port is programmed as an input, reading it through the GPI/O register latches either the inverted or non-inverted logic value present at the GPI/O pin; writing it has no Table 50 - ...
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There are three system events which can reset the WDT; these are a keyboard interrupt, a mouse interrupt, or I/O reads/writes to address 0x201 (the internal or an external joystick Port). The effect on the WDT for each of these ...
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Table 52 - Watchdog Timer/Power LED Configuration Registers CONFIG REG. BIT FIELD WDT_VAL Bits[7:0] WDT_CFG Bit[0] Bit[1] Bit[2] Bit[3] Bits[7:4] WDT_CTRL Bit[0] Bit[1] Bit[2] Bit[3] Bit[4] Bit[5,6,7] GENERAL PURPOSE ADDRESS DECODER General Purpose I/O pin GP14 may be configured as ...
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GP16 JOYSTICK FUNCTION The FDC37C93xAPM may be configured to generate either a Joystick Chip Select or a Joystick Read Strobe on GP16. The polarity is programmable through a bit in the GP16 confiugration register. When configured as a Joystick Chip ...
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BIT Reserved, set to zero. Serial EEPROM Pointer Register, 0xF2 BIT Use this register to set the Serial EEPROM's pointer. The value in this register always reflects the current EEPROM pointer address. The Serial ...
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GATEA20 GATEA20 is an internal signal from the Keyboard controller (Port FDC37C93xAPM may be configured to drive this signal onto GP25 by programming its GPI/O Configuration Register. See the 8042 Keyboard Controller Section for more information. EITHER EDGE TRIGGERED INTERRUPTS ...
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KEYBOARD CONTROLLER AND REAL TIME CLOCK FUNCTIONAL The FDC37C93xAPM is a Ultra I/O, Real Time Clock and Universal Keyboard Controller de- signed for intelligent keyboard management in desktop computer applications. The Ultra I/O supports a floppy disk controller, two ...
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KEYBOARD AND RTC ISA INTERFACE The FDC37C93xAPM ISA functionally compatible with the 8042-style host interface. It consists of the D0-7 data bus, the nIOR, nIOW and the Status Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN ISA ADDRESS ...
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RTC Data Register A read of this register will read the contents of the selected CMOS register. A write to this register will write to the selected CMOS register. 8042 INSTRUCTION OUT DBB Set OBF, and, if enabled, the KIRQ ...
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EXTERNAL KEYBOARD AND INTERFACE Industry-standard PC/AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission. Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expansion, the FDC37C93xAPM provides four signal pins ...
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Host I/F Status Register The Status register is 8 bits wide. Table 55 shows the contents of the Status register Status Register This register is cleared on a reset. This register is read-only for ...
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DESCRIPTION KCLK KDAT MCLK MDAT Host I/F Data Reg Host I/F Status Reg RTCCNTRL RTCADDR RTCDATA NC: No Change N/A: Not Applicable GATEA20 AND KEYBOARD RESET The FDC37C93xAPM provides several options for GateA20 and Keyboard Software Generated GateA20 and KRESET, ...
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BIT 7:6 Reserved. Returns 00 when read. 5 Reserved. Returns a 1 when read. 4 Reserved. Returns a 0 when read. 3 Reserved. Returns a 0 when read. 2 Reserved. Returns a 1 when read. 1 ALT_A20 Signal control. Writing ...
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This pulse is output on pin KRESET and its polarity is controlled by the 14us 8042 P20 FE Command Pulse Gen KRST_GA20 Bit 0 KRST_GA20 P92 Bit 0 Pulse Gen Note: When Port 92 is disabled, writes ...
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KRST_GA20 Bit 1 A nIOW DD1 DFF Address DFE KRST_GA20 Bit 0 nAEN&60 DD1 After D1 nIOW nAEN&64 nIOW D nAEN&60 Trailing Edge Delay A nIOW 24MHz FIGURE 8 - GATEA20 GENERATION LOGIC The timing for a D1 command ...
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CLK AEN nAEN 64=I/O Addr n64 nIOW nA DD1 nDD1 nCNTL nIOW' nIOW+n64 AfterD1 nAfterD1 60=I/O Addr n60 nIOW+n60=B nAfterD1+B D[1] GA20 FIGURE 9 - GATE A20 TURN-ON SEQUENCE TIMING When writing to the command and data port with ...
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FAST GATEA20 AND KEYBOARD RESET GATEA20/KRESET Hardware Speed-Up The FDC37C93xAPM contains on-chip logic support for the GATEA20 and NAME REG INDEX KRST_GA20 0xF0 When the chip receives a "D1" command followed by data (via the host interface), the on- chip ...
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Table 60 - GATEA20 Command/Data Sequence Examples SA2 R/W D[0: D[1]= D[1]= D[1]= ...
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REAL TIME CLOCK The Real Time Clock is a complete time of day clock with two alarms, calendar (up to the year 9999), a programmable periodic interrupt, and a programmable square wave generator. Features Counts seconds, minutes, and hours of ...
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RTC Interrupt The interrupt generated by the RTC is an active high output. The RTC interrupt output remains high as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set. RESET_DRV or reading ...
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Table 62B shows Bank 1, the second bank of CMOS registers which contains an additional 128 bytes of general purpose CMOS registers. Table 62B - Real Time Clock Address Map, Bank 1 ADDRESS REGISTER TYPE 0-7F R/W Table 62C shows ...
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PM when "1". Once per second, the ten time, calendar and alarm 1 bytes as well as the century byte and seven alarm 2 ...
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Table 63A - Time, Calendar and Alarm 1 Bytes ADD REGISTER FUNCTION 0 Register 0: Seconds 1 Register 1: Seconds Alarm 2 Register 2: Minutes 3 Register 3: Minutes Alarm 4 Register 4: Hours (12 hour mode) (24 hour mode) ...
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These bits function as follows: If VTR is present: AL2_EN controls whether or not alarm 2 is enabled as a wake-up function. If AL2_EN ...
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INPUT CLOCK FREQUENCY UIP BIT 32.768 kHz 32.768 kHz CONTROL AND STATUS REGISTERS, BANK 0 Bank 0 of the RTC has four registers which are accessible to the processor program at all REGISTER A (AH) MSB UIP ...
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Table 65 - Divider Selection Bits REGISTER A BITS OSCILLATOR FREQUENCY DV2 DV1 32.768 KHz 0 32.768 KHz 0 32.768 KHz 0 32.768 KHz 0 32.768 KHz 1 1 Table 66 - Periodic Interrupt Rates RATE SELECT RS3 RS2 RS1 ...
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REGISTER B (BH) MSB SET PIE AIE SET When the SET bit is a "0", the update functions normally by advancing the counts once per second. When the SET bit is a "1", an update cycle in ...
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REGISTER C (CH) - READ ONLY REGISTER MSB IRQF PF AF IRQF The interrupt request flag is set to a "1" when one or more of the following are true PIE = ...
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REGISTER D (DH) READ ONLY REGISTER MSB VRT 0 0 VRT When a "1", this bit indicates that the contents of the RTC are valid. A "0" appears in the VRT bit when the battery voltage is ...
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Control Registers, Bank 2 Bank 2 of the RTC has one control register AL2_REM_EN - One of the two control bits for the Alarm 2 wakeup function the “remember” enable bit for ...
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Power Supply Operational Modes Note: See the Operational Description Section for the Power Supply Operational Modes. Power Management The RAMD signal controls all bus inputs to the RTC and RAM (nIOW, nIOR, RESET_DRV). When asserted, it disallows any modification of ...
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SOFT POWER MANAGEMENT The FDC37C93xAPM employs management to allow the chip to enter low power mode and to provide a variety of wakeup events to power up the chip. allows for software control over powerdown and wakeup events. In low ...
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Soft Power Mangement OFF_EN OFF_DLY Button L Button Input ED; PG SP1 ED; L EN1 nSPOFF1 SPx ED; L ENx nSPOFF1 PWRBTNOR_EN A transition on the Button input or on any enabled SPx inputs causes the nPowerOn output to go ...
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REGISTERS The following registers can be accessed when in configuration mode at Logical Registers B0-B3, B8 and F4, and when not in configuration they can be accessed through the Index and Data Register. Soft Power Enable Registers Soft Power Enable ...
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The power button has an override event as required by the ACPI specification. If the user presses the power button for more than four seconds while the system is in the working state, a hardware event is generated and the ...
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SYSTEM MANAGEMENT INTERRUPT (SMI) The FDC37C93xAPM implements a group nSMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for transparent management. The nSMI group interrupt output consists of the enabled interrupts from ...
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The FDC37C93xAPM supports ACCESS.bus. ACCESS.bus is a serial communication protocol between a computer host and its peripheral devices. It provides a simple, uniform and inexpensive way to connect peripheral devices to a single computer port. A single ACCESS.bus on a ...
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Table 68 - ACCESS.BUS Control/Status Register S1: Control Bit Def PIN ES0 Status Bit Def PIN 0 Bit Definitions Register S1 Control Section The write-only section of S1 enables access ...
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Note 1: In master receiver mode, the last byte must be terminated with ACK bit high (‘negative acknowledge’) Note 2: If both STA and STO are set high simultaneously in master mode, a STOP condition followed by a START condition ...
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In transmitter mode, PIN is set to logic “1” (inactive) each time register S0 is written. In receiver mode, PIN is set to logic “0” (inactive) on completion of ...
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Own Address Register S0’ When the chip is addressed as slave, this register must be loaded with ACCESS.bus address to which the chip is to respond. During initialization, the own address register S0’ must be written to, regardless whether it ...
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Clock Register S2 Register S2 controls the selection of the internal chip clock frequency used RST RESERVED Default = 00 at hard reset and power on reset. BIT 7: AB_RST ACCESS.bus Reset Bit. This bit ...
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ADVANCED CONFIGURATION AND POWER INTERFACE The FDC37C93xAPM supports the Advanced Configuration and Power Interface (ACPI) as described in this section. LEGACY/ACPI SELECT CAPABILITY This capability consists of an SMI/SCI switch which is required if the system supports both legacy and ...
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GBL_STS bit. Writing a “0” to BIOS_RLS has no effect. Writing a “0” to GBL_STS has no effect. The GBL_RLS bit is used ...
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Bus Master The Bus Master event logic is shown in Figure 14. The BM_RLD and BM_STS bits are located in the PM1_BLK and BM_CNTRL is located in the MSC_BLK. These bits are described below ...
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POWER MANAGEMENT TIMER This is a 24-bit free running timer that is required for ACPI compliance. management timer provides an accurate time function while the system is in the working state. This feature is a 24-bit counter which runs off ...
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POWER BUTTON OVERRIDE EVENT The power button has an override event as required for ACPI compliance. Power Management Section. If the user presses the power button for more than four seconds while the system is in the working state, a ...
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Table 71A and 71B list the MSCregister blocks and the locations of the registers contained in these blocks. All of these REGISTER PM1_STS 1 PM1_STS 2 PM1_EN 1 PM1_EN 2 PM1_CNTRL 1 PM1_CNTRL 2 Reserved Reserved PM1_TMR 1 PM1_TMR 2 ...
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Power Management 1 Register Block (PM1_BLK) The registers in this block are powered by VTR. Power Management 1 Status Register 1 (PM1_STS 1) Register Location: <PM1_BLK> System I/O Space Default Value: 00h on VTR POR Attribute: Read/Write (Note 0) Size: ...
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Power Management 1 Status Register 2 (PM1_STS 2) Register Location: <PM1_BLK>+1h System I/O Space Default Value: 00h on VTR POR Attribute: Read/Write (Note 0) Size: 8 bits Table 73 - Power Management 1 Status Register 2 BIT NAME 0 PWRBTN_ST ...
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Power Management 1 Enable Register 1 (PM1_EN 1) Register Location: <PM1_BLK>+2 System I/O Space Default Value: 00h on VTR POR Attribute: Read/Write (Note 0) Size: 8 bits Table 74 - Power Management 1 Enable Register 1 BIT NAME 0 TMR_EN ...
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Power Management 1 Control Register 1 (PM1_CNTRL 1) Register Location: <PM1_BLK>+4 System I/O Space Default Value: 00h on VTR POR Attribute: Read/Write (Note 0) Size: 8 bits Table 76 - Power Management 1 Control Register 1 BIT NAME 0 SCI_EN ...
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Power Management 1 Timer 1 (PM1_TMR 1) Register Location: <PM1_BLK>+8h System I/O Space Default Value: 00h on VTR POR and RESET_DRV Attribute: Read-Only Size: 8 bits Table 78 - Power Management 1 Timer 1 BIT NAME 0-7 TMR_VAL This read-only ...
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Power Management 1 Timer 3 (PM1_TMR 3) Register Location: <PM1_BLK>+Ah System I/O Space Default Value: 00h on VTR POR and RESET_DRV Attribute: Read-Only Size: 8 bits Table 80 - Power Management 1 Timer 3 BIT NAME 0-7 TMR_VAL This read-only ...
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Miscellaneous Block (MSC_BLK) The registers in this block are powered by VTR. SCI Status Register 1 (SCI_STS1) This register is used to read the status of the SCI inputs. Register Location: <MSC_BLK>+0h System I/O Space Default Value: N/A (Status Bits ...
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SCI Enable Register 1 (SCI_EN1). This register is used to enable the different interrupt sources onto the group SCI output, and the group SCI output onto an IRQ pin for SCI. Register Location: <MSC_BLK>+2h System I/O Space Default Value: 00h ...
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Miscellaneous Status Register (MSC_STS) Register Location: <MSC_BLK>+4h System I/O Space Default Value: 02h on VTR POR Attribute: Read/Write (Note 0) Size: 8 bits Table 86 - Miscellaneous Status Register BIT NAME 0 BIOS_STS This bit is set when GBL_RLS is ...
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Miscellaneous Control Register (MSC_CNTRL) Register Location: <MSC_BLK>+7h System I/O Space Default Value: 00h on VTR POR Attribute: Read/Write (Note 0) Size: 8 bits Table 88 - Miscellaneous Control Register BIT NAME 0 BIOS_RLS This bit is used by the BIOS ...
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The configuration of the FDC37C93xAPM is very flexible and is based on the configuration architecture implemented in typical Plug-and- Play components. The FDC37C93xAPM is designed for motherboard applications in which the resources required by their components are known. With its ...
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CONFIGURATION SEQUENCE To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. Enter Configuration Mode To place the chip Configuration State the Config Key is sent ...
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Notes: 1. HARD RESET: RESET_DRV pin asserted 2. SOFT RESET: Bit 0 of Configuration Control register set to one 3. All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram) Table 90 - Configuration Registers HARD ...
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Table 90 - Configuration Registers HARD RESET INDEX TYPE / V POR CC LOGICAL DEVICE 1 CONFIGURATION REGISTERS (IDE1) 0x30 R/W 0x00 0x60, R/W 0x01, 0x61 0xF0 0x62, R/W 0x03, 0x63 0xF6 0x70 R/W 0x0E 0xF0 R/W 0x0C 0xF1 R/W ...
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Table 90 - Configuration Registers HARD RESET INDEX TYPE / V POR CC LOGICAL DEVICE 5 CONFIGURATION REGISTERS (Serial Port 2) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 0x70 R/W 0x00 0xF0 R/W 0x00 0xF1 R/W 0x02 0xF2 R/W ...
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Table 90 - Configuration Registers HARD RESET INDEX TYPE / V POR CC 0x61 0x62, R/W 0x00, 0x63 0x00 0xB0 R/W 0xB1 R/W 0xB2 R/W 0xB3 R/W 0xB4 R/W 0xB5 R/W 0xB6 R/W 0xB7 R/W 0xB8 R/W 0xC0 R/W 0xC1 ...
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Table 90 - Configuration Registers HARD RESET INDEX TYPE / V POR CC 0xD6 R/W 0xD7 R/W 0xD8 R/W 0xD9 R/W 0xDA R/W 0xDB R/W 0xDC R/W 0xDD R/W 0xDE R/W 0xDF R/W 0xE0 R/W 0xE1 R/W 0xE2 R/W 0xE3 ...
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Table 90 - Configuration Registers HARD RESET INDEX TYPE / V POR CC 0xF6 R/W 0x00 0xF7 R/W 0x00 0xF8 R/W 0x00 0xF9 R/W 0x00 0xFA R/W 0x00 0xFB R/W 0x00 LOGICAL DEVICE 9 CONFIGURATION REGISTERS (ACCESS.bus) 0x30 R/W 0x00 ...
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Chip - Level (Global) Control/Configuration Registers [0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return ...
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REGISTER ADDRESS Logical Device # 0x07 R/W Default = 0x00 on V POR or CC Reset_Drv Card Level 0x08 - 0x1F Reserved - Writes are ignored, reads return 0. Reserved Device ID 0x20 R Hard wired = 0x30 Device Rev ...
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REGISTER ADDRESS OSC 0x24 R/W Default = 0x04 POR or CC Reset_Drv hardware signal. Chip Level 0x25 Vendor Defined Configuration 0x26 Address Byte 0 Default =0 F0 (Sysopt= (Sysopt= POR or CC ...
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REGISTER ADDRESS Default = 0x00 on V POR and CC Hard Reset Chip Level 0x29 -0x2C Reserved - Writes are ignored, reads return 0. Vendor Defined TEST 1 0x2D R/W TEST 2 0x2E R/W TEST 3 0x2F R/W Default = ...
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Logical Device Configuration/Control Registers [0x30-0xFF] Used to access the registers that are assigned to each logical unit. This chip supports nine logical units and has nine sets of logical device registers. The nine logical devices are Floppy, IDE1, IDE2, Parallel, ...