SA-1100 Intel Corporation, SA-1100 Datasheet
SA-1100
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SA-1100 Summary of contents
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... The SA-1100 incorporates a 32-bit StrongARM at 133/190 MHz with instruction and data cache, memory-management unit (MMU), and read/write buffers. In addition, the SA-1100 provides system support logic, multiple serial communication channels, a color/gray scale LCD controller, PCMCIA support for up to two sockets, and general- purpose I/O ports ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1999 *Other brands and names are the property of their respective owners. ARM and StrongARM are registered trademarks of ARM, Ltd. 2 SA-1100 Brief Datasheet ...
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... The SA-1100 also provides a write buffer and a read buffer. The read buffer allows critical data to be prefetched under software control, preventing pipeline stalls from occurring during external memory reads ...
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... Burst reads occur words (beats) as determined by the data destination within the SA-1100 (cache line fill, read buffer, or DMA). Burst writes occur words, depending on the final destination of the data outside the SA-1100 (write buffer, DMA). When a castout is occurring from cache, the SA-1100 will perform an 8-word write for a full 32 bytes ...
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... SDLC and UART are required in a given system, two GPIO pins can be configured to perform the UART RX/TX functionality, leaving the TX_2/RX_2 pins free for SDLC. Serial port 2 on the SA-1100 provides logic to support infrared data (IrDA) at either 115 Kbps or 4 Mbps. The low-speed IrDA utilizes the HP-SIR the 4 PPM standard ...
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... The I/O ring runs at 3 allow simple system interconnections. Another key element in the SA-1100 power strategy is the use of independent conditional clocking trees, which ensure that only currently required units are clocked and other units remain static. The SA-1100 may be run at a variety of frequencies, ranging from 39 MHz up to 190 MHz. ...
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... Figure 1. Block Diagram of the SA-1100 3.686 PLL OSC MHz 32.768 OSC KHz RTC OS Timer General- Purpose I/O Interrupt Controller Power Management Reset Controller Channel 0 * ARM and StrongARM are registered trademarks of ARM Limited. SA-1100 Brief Datasheet Instruction PC Icache IMMU (16 Kbytes) Dcache Addr DMMU ...
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... Package nomenclature as been modified due to industry standardization of packages. LQFP is 1.4 mm thick, thin quad flat pack. Please note that no modification has been made to the package itself. For information on order numbers, see the SA-1100 Linecard in the StrongARM products section of Intel’s web site for developers. ...
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Support, Products, and Documentation If you need general information or support, call 1-800-628-8686 or visit Intel’s website at: http://www.intel.com Copies of documents that have an ordering number and are referenced in this document, a product catalog, or other Intel literature ...