MT48LC4M32B2 Micron Semiconductor Products, MT48LC4M32B2 Datasheet

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MT48LC4M32B2

Manufacturer Part Number
MT48LC4M32B2
Description
SYNCHRONOUS DRAM
Manufacturer
Micron Semiconductor Products
Datasheet
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
• Internal pipelined operation; column address can
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3.
OPTIONS
• Configuration
• Package - OCPL
• Timing (Cycle Time)
• Operating Temperature Range
NOTE: 1. Off-center parting line
KEY TIMING PARAMETERS
*CL = CAS (READ) latency
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
GRADE
SPEED
positive edge of system clock
be changed every clock cycle
PRECHARGE, and Auto Refresh Modes
4 Meg x 32 (1 Meg x 32 x 4 banks)
86-pin TSOP (400 mil)
6ns (166 MHz)
7ns (143 MHz)
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
-6
-7
2. Available on -7
FREQUENCY
166 MHz
143 MHz
CLOCK
MT48LC4M32B2TG-7
Part Number Example:
1
ACCESS TIME
CL = 3*
5.5ns
5.5ns
SETUP
TIME
1.5ns
2ns
MARKING
4M32B2
None
IT
TG
-6
-7
HOLD
TIME
1ns
1ns
2
1
MT48LC4M32B2 - 1 Meg x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
Note: The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
www.micron.com/sdramds
PIN ASSIGNMENT (TOP VIEW)
DQM0
DQM2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
V
V
V
V
CAS#
RAS#
V
V
V
V
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DD
DD
DD
DD
A11
BA0
BA1
A10
V
V
V
V
CS#
SS
SS
SS
SS
NC
NC
A0
A1
A2
DD
DD
DD
DD
Q
Q
Q
Q
Q
Q
Q
Q
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86-PIN TSOP
1 Meg x 32 x 4 banks
4 Meg x 32
4 (BA0, BA1)
4K (A0–A11)
256 (A0–A7)
4K
128Mb: x32
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
©2002, Micron Technology, Inc.
SDRAM
V
DQ15
V
DQ14
DQ13
V
DQ12
DQ11
V
DQ10
DQ9
V
DQ8
NC
V
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
NC
DQ31
V
DQ30
DQ29
V
DQ28
DQ27
V
DQ26
DQ25
V
DQ24
V
SS
SS
DD
SS
DD
SS
SS
DD
SS
DD
SS
SS
Q
Q
Q
Q
Q
Q
Q
Q

Related parts for MT48LC4M32B2

MT48LC4M32B2 Summary of contents

Page 1

... 166 MHz 5.5ns -7 143 MHz 5.5ns *CL = CAS (READ) latency 128Mb: x32 SDRAM 128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02 MT48LC4M32B2 - 1 Meg banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds PIN ASSIGNMENT (TOP VIEW) MARKING 4M32B2 ...

Page 2

... SDRAM PART NUMBER PART NUMBER ARCHITECTURE MT48LC4M32B2TG 4 Meg x 32 GENERAL DESCRIPTION The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits ...

Page 3

TABLE OF CONTENTS Functional Block Diagram - 4 Meg x 32 .................. Pin Descriptions ...................................................... Functional Description ...................................... Initialization ...................................................... Register Definition ............................................. Mode Register .............................................. Burst Length ............................................ Burst Type ............................................... Operating Mode ..................................... Write Burst Mode ................................... CAS ...

Page 4

CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 8 128Mb: x32 SDRAM 128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02 FUNCTIONAL BLOCK DIAGRAM 4 Meg x 32 SDRAM BANK0 12 ...

Page 5

PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE 68 CLK 67 CKE 20 CS# 17, 18, 19 WE#, CAS#, RAS# 16, 71, 28, 59 DQM0– DQM3 22, 23 BA0, BA1 Input 25-27, 60-66, 24, 21 A0-A11 10, ...

Page 6

PIN DESCRIPTIONS (continued) PIN NUMBERS SYMBOL TYPE 14, 30, 57, 69, 70 35, 41, 49 12, 32, 38, 46 15, 29 ...

Page 7

FUNCTIONAL DESCRIPTION In general, this 128Mb SDRAM (1 Meg banks quad-bank DRAM that operates at 3.3V and in- cludes a synchronous interface (all signals are regis- tered on the positive edge of the clock ...

Page 8

BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is deter- mined ...

Page 9

CAS Latency The CAS latency is the delay, in clock cycles, be- tween the registration of a READ command and the availability of the first piece of output data. The la- tency can be set to one, two or three ...

Page 10

Commands Truth Table 1 provides a quick reference of avail- able commands. This is followed by a written descrip- tion of each command. Three additional Truth Tables TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) COMMAND ...

Page 11

COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, re- gardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The ...

Page 12

BURST TERMINATE The BURST TERMINATE command is used to trun- cate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of ...

Page 13

Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be is- sued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the AC- TIVE command, which selects both the bank ...

Page 14

READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are pro- vided with the READ command, and auto precharge is either enabled or disabled for that burst access. If ...

Page 15

This 128Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch ...

Page 16

CLK COMMAND ADDRESS DQ CAS Latency = 1 CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. 128Mb: x32 SDRAM 128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02 Figure 8 Random ...

Page 17

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turn- around limitations). The WRITE burst ...

Page 18

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not acti- vated), and a full-page burst may be truncated with a PRECHARGE command to the same ...

Page 19

The disadvantage of the PRECHARGE command is that it requires that the com- mand and address buses be available at the appropri- ate time to issue the command; ...

Page 20

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto ...

Page 21

Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by a READ command. Once the READ command is regis- tered, the data inputs will ...

Page 22

Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coin- cident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM ...

Page 23

CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge ...

Page 24

CONCURRENT AUTO PRECHARGE An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four ...

Page 25

WRITE WITH AUTO PRECHARGE 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out ap- pearing CAS latency later. The PRECHARGE to bank ...

Page 26

TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...

Page 27

TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L L ...

Page 28

NOTE (continued): Write w/Auto Precharge Enabled: 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an ...

Page 29

TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row L ...

Page 30

NOTE (continued): 4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...

Page 31

ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V .............................................. -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V .............................................. -1V to +4.6V SS Operating Temperature ............................ ...

Page 32

CAPACITANCE (Note: 2) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11; notes appear on page 34) AC CHARACTERISTICS PARAMETER Access time from ...

Page 33

AC FUNCTIONAL CHARACTERISTICS (Notes 11; notes appear on page 34) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to ...

Page 34

NOTES 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V can range from 0pF to 6pF dependent on ...

Page 35

INITIALIZE AND LOAD MODE REGISTER CLK ( ( ) ) t CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ( ) ) COMMAND ...

Page 36

CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all All banks ...

Page 37

CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM0 A0-A9, A11 COLUMN ...

Page 38

T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active ...

Page 39

T0 T1 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP DQM 0-3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active ...

Page 40

SINGLE READ – WITHOUT AUTO PRECHARGE T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 ...

Page 41

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0-A9, A11 ROW A10 DISABLE AUTO PRECHARGE t ...

Page 42

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 ...

Page 43

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 ROW A0-A9, A11 ENABLE AUTO PRECHARGE ROW A10 ...

Page 44

CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS DQM 0 A0-A9, A11 COLUMN m 2 ROW ...

Page 45

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0-A9, A11 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...

Page 46

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQM / DQML, DQMH A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...

Page 47

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 A0-A9, A11 ROW ROW A10 DISABLE AUTO PRECHARGE ...

Page 48

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP WRITE t CMS DQM 0 A0-A9, A11 COLUMN m 3 ROW ENABLE AUTO ...

Page 49

ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM 0 COLUMN m 3 ROW A0-A9, A11 ...

Page 50

CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ROW A10 BA0, BA1 ...

Page 51

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...

Page 52

TYP 0.20 R .75 (2X) PIN # 1.00 (2X) 1. All dimensions in millimeters MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.025mm ...

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