MT4LC4M4E8TG-5 Micron Semiconductor Products, MT4LC4M4E8TG-5 Datasheet

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MT4LC4M4E8TG-5

Manufacturer Part Number
MT4LC4M4E8TG-5
Description
4Meg x 4 banks, EDO DRAM, 3.3V, standard refresh, 50ns
Manufacturer
Micron Semiconductor Products
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
MT4LC4M4E8TG-5
Manufacturer:
MICRON
Quantity:
53
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
• State-of-the-art, high-performance, low-power CMOS
• Single power supply (+3.3V 0.3V or +5V 10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
• Voltages
• Refresh Addressing
• Packages
• Timing
• Refresh Rates
• Part Number Example: MT4LC4M4E8DJ-6
KEY TIMING PARAMETERS
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
SPEED
packages
silicon-gate process
BEFORE-RAS# (CBR)
12 row, 10 column addresses (4K refresh)
3.3V
5V
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
50ns access
60ns access
Standard Refresh
Self Refresh (128ms period)
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates V
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
-5
-6
104ns
84ns
t
RC
TECHNOLOGY, INC.
50ns
60ns
t
RAC
CC
= 3.3V and C designates V
20ns
25ns
t
PC
25ns
30ns
t
AA
CC
MARKING
= 5V. The fifth field
13ns
15ns
t
CAC
None
LC
TG
E8
E9
DJ
-5
-6
C
S
10ns
t
8ns
CAS
1
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
GENERAL DESCRIPTION
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
4 MEG x 4 EDO DRAM PART NUMBERS
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
PART NUMBER
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
*NC/A11
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
RAS#
WE#
DQ1
DQ2
A10
V
V
24/26-Pin SOJ
A0
A1
A2
A3
CC
CC
PIN ASSIGNMENT (Top View)
1
2
3
4
5
6
8
9
10
11
12
13
(DA-2)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
26
25
24
23
22
21
19
18
17
16
15
14
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Vcc
5V
5V
5V
5V
5V
5V
5V
5V
V
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
SS
REFRESH
*NC/A11
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
RAS#
WE#
DQ1
DQ2
V
A10
V
24/26-Pin TSOP
A0
A1
A2
A3
CC
CC
1
2
3
4
5
6
8
9
10
11
12
13
PACKAGE
EDO DRAM
(DB-2)
TSOP
TSOP
TSOP
TSOP
TSOP
TSOP
TSOP
TSOP
SOJ
SOJ
SOJ
SOJ
SOJ
SOJ
SOJ
SOJ
4 MEG x 4
1997, Micron Technology, Inc.
26
25
24
23
22
21
19
18
17
16
15
14
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
REFRESH
Self
Self
Self
Self
Self
Self
Self
Self
V
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
SS

Related parts for MT4LC4M4E8TG-5

MT4LC4M4E8TG-5 Summary of contents

Page 1

... MARKING * refresh and A11 on 4K refresh options. Note: The “#” symbol indicates signal is active LOW MEG x 4 EDO DRAM PART NUMBERS E8 PART NUMBER E9 MT4LC4M4E8DJ MT4LC4M4E8DJS DJ MT4LC4M4E8TG TG MT4LC4M4E8TGS MT4LC4M4E9DJ -5 MT4LC4M4E9DJS -6 MT4LC4M4E9TG MT4LC4M4E9TGS None MT4C4M4E8DJ S MT4C4M4E8DJS MT4C4M4E8TG MT4C4M4E8TGS MT4C4M4E9DJ = 5V. The fifth field ...

Page 2

TECHNOLOGY, INC. GENERAL DESCRIPTION (continued) (the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are “don’t care”). READ and WRITE cycles are selected with the WE# input. A logic HIGH on ...

Page 3

TECHNOLOGY, INC. Figure 1). WE# can also perform the function of disabling the output devices under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle ...

Page 4

TECHNOLOGY, INC. FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH WE# CAS# NO. 2 CLOCK GENERATOR COLUMN ADDRESS 11 A0 BUFFER(11 REFRESH A3 CONTROLLER REFRESH A7 COUNTER A10 ROW ADDRESS 11 BUFFERS (11) NO. ...

Page 5

TECHNOLOGY, INC. TRUTH TABLE FUNCTION Standby READ EARLY WRITE READ WRITE EDO-PAGE-MODE 1st Cycle READ 2nd Cycle EDO-PAGE-MODE 1st Cycle EARLY WRITE 2nd Cycle Any Cycle EDO-PAGE-MODE 1st Cycle READ-WRITE 2nd Cycle HIDDEN READ REFRESH WRITE RAS#-ONLY REFRESH CBR REFRESH ...

Page 6

TECHNOLOGY, INC. ABSOLUTE MAXIMUM RATINGS* Voltage on V Pin Relative 3.3V ................................................................ -1V to +4.6V 5V ...................................................................... -1V to +7V Voltage on NC, Inputs or I/O Pins Relative to V 3.3V ................................................................ -1V to +5.5V 5V ...

Page 7

TECHNOLOGY, INC. Icc OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (non-S version only) (RAS# = CAS# = other inputs = V STANDBY CURRENT: CMOS ...

Page 8

TECHNOLOGY, INC. CAPACITANCE PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12, 17 CHARACTERISTICS PARAMETER Access time from column address Column address ...

Page 9

TECHNOLOGY, INC. AC ELECTRICAL CHARACTERISTICS (Notes 10, 11, 12, 17 CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from ...

Page 10

TECHNOLOGY, INC. NOTES 1. All voltages referenced The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚ initial pause of 100 ...

Page 11

TECHNOLOGY, INC RAS CRP V CAS ASR V IH ROW ADDR WE OE TIMING PARAMETERS -5 ...

Page 12

TECHNOLOGY, INC RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL TIMING PARAMETERS -5 ...

Page 13

TECHNOLOGY, INC. (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL V IH OE# ...

Page 14

TECHNOLOGY, INC RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR V ROW OPEN ...

Page 15

TECHNOLOGY, INC. EDO-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE ...

Page 16

TECHNOLOGY, INC. (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW WE RAC ...

Page 17

TECHNOLOGY, INC. EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH ...

Page 18

TECHNOLOGY, INC RAS CRP V CAS ASR V IH ADDR WE OE TIMING PARAMETERS -5 SYMBOL ...

Page 19

TECHNOLOGY, INC RAS CRP V IH CAS ASR V IH ADDR RAS RPC CSR V ...

Page 20

TECHNOLOGY, INC RAS CRP CAS ASR t RAH V IH ADDR ROW OE TIMING PARAMETERS -5 SYMBOL MIN MAX ...

Page 21

TECHNOLOGY, INC RAS RPC CSR V IH CAS WRP TIMING PARAMETERS -5 SYMBOL MIN MAX t CHD ...

Page 22

TECHNOLOGY, INC. .305 (7.75) .299 (7.59) .340 (8.64) .330 (8.38) PIN #1 INDEX .050 (1.27) TYP .600 (15.24) TYP .037 (0.94) MAX DAMBAR PROTRUSION SEATING PLANE NOTE: 1. All dimensions in inches (millimeters) 2. Package width and length do not ...

Page 23

TECHNOLOGY, INC. .678 (17.23) .672 (17.07) PIN #1 INDEX .050 (1.27) TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per ...

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