QQ84C300A LSI Computer Systems, Inc., QQ84C300A Datasheet
QQ84C300A
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QQ84C300A Summary of contents
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Features Low Power CMOS Technology 4-Port Ethernet Controller Optimized for Switching Hub, Multiport Bridge/Router, Server Applications Supports 100Base-T4, 100 Base-TX, 100Base-FX & 10Base-T Transceivers Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards for Thicknet (10Base-5), Thin Net (10Base-2) and Twisted Pair ...
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Table of Contents 1.0 Pin Description 2.0 Introduction 3.0 Functional Description 3.1 Frame Format 3.2 Packet Transmission per Port 3.2.1 Controlling Transmit Packet Encapsulation 3.2.2 Transmission Initiation/Deferral 3.2.3 Collision on Transmit 3.2.4 Transmit Termination Conditions 3.2.5 Conditions That Will Cause ...
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Pin Description Pin Pin Name I/O Chip Registers’ Interface 22 I ENREGIO 21, 20 REGPS[1:0] I 153, A[3: 9-12 CDST[7:0] I/O 15-18 47, 61, INT_[1:4] O 68, ...
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Pin Description (cont.) Pin Pin Name I/O Receive and Transmit FIFO Interface 31 I Receive Interface Enable RXINTEN This is an active low input that acts as a chip enable to enable the receiver interface. Driving this pin active enables ...
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Pin Description (cont.) Pin Pin Name I/O 44, 57 TXRDY_ [1:4] O 64, 73 42, 56 RXRDY_ [1: SPDTAVL O 40 RXTXEOF I/O 41 TXNOCRC ...
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Pin Description (cont.) Pin Pin Name I/O Transmit and Receive Exception Indicators 48, 62 TXRET_ [1:4] O Transmit Retry 71, 79 These are active high tristate outputs. All four of these output pins are driven by tristate drivers enabled by ...
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Pin Description (cont.) Pin Pin Name I/O Media Independent Interface 138 TXC_1 I 161 TXC_2 I 177 TXC_3 I 197 TXC_4 I 139-142 TXD[3:0]_1 O 162, 163 TXD[3: 164, 166 180, 181 TXD[3: 182, 185 MD400152/E ...
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Pin Description (cont.) Pin Pin Name I/O 198, 199 TXD[3: Transmit Data Port 4 201, 202 In standard 10 Mbit/sec Serial Mode, TXD0_4 is the serial transmit data output from port #4 to the encoder. In MII mode, ...
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Pin Description (cont.) Pin Pin Name I/O 169 RXC_3 I 188 RXC_4 I 131, 133 RXD[3:0]_1 I 136, 137 149, 150 RXD[3:0]_2 I 151, 160 172-175 RXD[3:0]_3 I 192 RXD[3:0]_4 I 194-196 130 CSN_1 I 129 RX_DV_1 I 148 CSN_2 ...
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Pin Description (cont.) Pin Pin Name I/O 147 RX_DV_2 I Receive Data Valid Port 2 In MII mode this input is receive data valid. Receive data valid becomes active with the first nibble of synchronized and decoded Preamble or SFD ...
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Pin Description (cont.) Pin Pin Name I/O 204 COLL_4 I 205 DAISY_OUT O 2, 14, 28, 33, V — DD 52, 53, 70, 78, 102, 104, 114, 126, 132, 135, 154, 157, 158, 178, 183, 189, 193 ...
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MD400152/E Fast Ethernet Controller 12 4-12 84C300A 4-Port ...
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GND -#1 #208 V DD GND CDST7 CDST6 -#10 CDST5 CDST4 GND V DD CDST3 CDST2 GND REGPS0 RXTXBE3 RXTXBE2 RXTXBE0 GND TXINTEN GND RXRDEN TXRET_1 GND Figure 2. 84C300A Pin Configuration MD400152/E Fast Ethernet ...
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Introduction The 84C300A is a 4-Port Ethernet Media Access Control- ler (MAC) with a rich set of operating modes and features manufactured as a single-chip VLSI device to simplify and enhance the development of multi-port Ethernet em- ...
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Preamble: The preamble is a 64-bit field consisting of 62 alternating “1”s and “0”s followed by a “11” End- of-Preamble indicator. Destination Address: The Destination Address is a 6-byte field containing either a specific Station Address, a Broadcast Address, or ...
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If the network is not busy due to other data traffic, transmission will begin after the appropriate defer time (from end of previous traffic) has expired. Otherwise, transmission is delayed until after current data transfers are complete, and the ...
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TRANSMIT DMA/ RECEIVE BUFFER DATA CONTROL BUFFER BUS TRANSCEIVER SYSTEM CPU MEMORY Figure 3. Typical Application Example 16 Transmission Attempts Collision occurs for the sixteenth consecutive time, the 16-Transmission- Attempts status bit is set, the Collision status bit ...
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TXRET flag is cleared. Similar to a port's receive discard signal, a transmit retry signal going to the external TXRET pin is latched upon a transmit retry condition and held high ...
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If the incoming frame is addressed to a port in the chip specifically (Destination Address matches the con- tents of the Station Address Register general or group interest (Broadcast or Multicast Address), the port will pass the ...
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Conditions that Cause the RXDC Pin to go HIGH As packets are discarded due to the receive packet error conditions given in section “3.3.5 Receive Discard Conditions”, the corresponding port’s RXDC pin may or may not assert receive ...
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CLRRXERR input high for a minimum of one RXRD_TXWR clock cycle. The RXINTEN input must not change state for the duration of the time that the CLRRXERR input is high. Clearing Interrupts Within one port, both receive and ...
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Valid combinations of the RXTXBE inputs for transmit FIFO writes are given below: RXTXBE3 RXTXBE2 RXTXBE1 RXTXBE0 ...
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Depending on the way RXRDEN is used, two different modes are possible, when the chip is used in the non- bidirectional byte enable mode. On burst reads (RXRDEN being asserted for multiple clock cycles), if the first read is not ...
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Internal Port Register Addressing Table Transmit Command Register Register Bits Address ...
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Bit 7 of station address byte 5 is compared to the last bit of the received destination address. The Station Address should be programmed prior to enabling a port’s receiver. 3.6.3 ...
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Transmit Status Register Within each port's transmit section are 2 transmit status registers. These registers give the appearance of a single register to an external CPU. With each transmission at- tempt, whether successful or not, one of the status ...
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Receive Command Register A port’s Receive Command Register has two primary functions, it specifies the Address Match Mode, and it specifies which types of receive frames will be received and if an associated interrupt will be produced. To set ...
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Match Match Mode Mode 1 0 Function Receiver Disable Receive All Frames Receive Station or Broadcast Frames Receive Station, Broadcast/Multicast Frames NOTE Changing the receive Match Mode bits ...
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Receive packet status is also included as part of the final double word of receive data for a packet that is not discarded. The final double word of a packet as read from the receive FIFO contains the status and ...
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Mode B: Transmit Packet Autopad Mode This feature automatically pads packets to be trans- mitted ...
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Configuration Register #2 Allows for control of a port’s transmission of one packet at a time, Busmode, Multi-cast hash filter, reception of runt frames, and halting new transmissions until one of the port’s transmit status registers is cleared. Mode A: ...
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CRC. If the corresponding bit is a ‘1’ it will receive the frame, otherwise it will discard the frame. Mode E: Receive Without ...
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FIFO Threshold Register This register allows programming of the threshold of Space Available and/or Data Available double word counts that cause assertion of the TxRDY and/or RxRDY signals respectively. Bits 4 through 7, when written with a binary value, ...
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Step 1: Calculation of the Actual Defer Time Let’s assume a Defer Register Setting Value of 10 Defer Time = Int{ {Int (Delay / 40 DefRegSet} / Int { { Int ( 8.5 ) ...
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COUNTERS CRC Error Counter This bit read only counter that counts the number of frames received or discarded with CRC errors but no framing errors. Upon reaching its maximum count value of FFFF hex, this counter ...
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ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. All voltages are specified with respect to GND, unless otherwise specified. 4.0 DC Characteristics ...
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AC Test Conditions Output Load: 1 Schottky TTL Gate + CL = 100 pF except where specifically given otherwise in the condition column. Input Pulse Level:0 2.4 V Timing Reference Level:1.5 V 5.0 COMMAND/STATUS INTERFACE TIMING AC Characteristics ...
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Command/Status Interface Read Timing RD TSEN ENREGIO TSPS REGPS[1:0] TSA A0-A3 CDST[7:0] DATA VALID 5.02 Command/Status Interface Write Timing WR TSEN ENREGIO REGPS[1:0] A0-A3 CDST[7:0] MD400152/E TRWL TRWH THPS THA TDBS TDBR TDBD THPS TSPS TSA THA TSCS 38 ...
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Ethernet Transmit and Receive Interface Timing AC Characteristics ETHERNET TRANSMIT INTERFACE TIMING Symbol Parameter TDTD TXD/TXEN Delay TWHTC TXC High Width TWLTC TXC Low Width ETHERNET RECEIVE INTERFACE TIMING THRD ...
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Transmit Data Interface Write Timing Symbol Parameter t Transmit Interface Enable 1 to Clock Setup Time t Transmit Write Enable 2 to Clock Setup Time t Transmit Interface Enable 3 to Transmit Write Enable Timing Skew t Port Select ...
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Transmit Data Interface Write Timing 1 RXRD_TXWR TXINTEN t 5 TXRDY RXTXPS[1:0] TXWREN RXTXDATA[31:0] RXTXBE[3:0] SPDTAVL TXNOCRC Notes: 1. SPDTAVL gets deasserted because of the 7th double word write to the transmit FIFO indicating that ...
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Transmit Data Interface Write Timing 2 RXRD_TXWR TXINTEN TXWREN RXTXBE[3:0] RXTXDATA[31:0] TXRDY SPDTAVL RXTXEOF TXNOCRC MD400152/E n-3 n-2 n n-3 n-2 n 4-42 84C300A 4-Port Fast Ethernet Controller n t14 n t ...
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Receive Data Interface Read Timing Symbol Parameter t Receive Interface Enable 1 to Clock Setup Time t Receive Read Enable 2 to Clock Setup Time t Receive Interface Enable 3 to Receive Read Enable Timing Skew t SPDTAVL Output ...
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Receive Data Interface Timing (cont’d) Symbol Parameter t RXRDY Deassert Due to Emptying 22 RX FIFO Below Threshold t RXRDY Assert from CSN Going 23 Low Due to Status Write 8.01 Receive Data Interface Read Timing RXRD_TXWR ...
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Receive Data Interface Read Timing 2 n-3 RXRD_TXWR RXINTEN RXRDY t 7 RXTXPS[1:0] RXRDEN RXTXDATA[31:0] RXTXBE[3:0] RXTXEOF CSN SPDTAVL MD400152/E n-2 n n-3 n-2 n-2 n 4-45 84C300A 4-Port Fast ...
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Transmit Data Interface Timing on Exception Conditions Symbol Parameter t TXINTEN Setup Time 1 t RXRD_TXWR to TXRET Delay 2 t TXRET Deassert from CLRTXERR 3 t TXWREN Setup Time 4 t TXWREN Hold Time 5 t CLRTXERR Setup ...
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Transmit Data Interface Timing on Exception Conditions (continued) Symbol Parameter t INT High to TXEN Low Delay 18 Due to Underflow TXEN Low to INT HIGH Delay Due to Carrier Sense Dropout TXEN Low to INT High Delay Due ...
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Receive Data Interface Timing on Exception Conditions Symbol Parameter t Receive INT Delay Due to 1 Shortframe, CRC, Good Frame, or Oversized Packet Receive INT Delay Due to Overflowed Packet t INT Clear Delay 2 t CLRRXERR Setup Time ...
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Receive Data Timing Diagram on Exception Conditions RXRD_TXWR RXINTEN RXRDY RXDC RXRDEN RXTXDATA[31:0] SPDTAVL RXABORT CLRRXERR INT RD_B MD400152 Invalid Invalid Invalid Invalid ...
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Reset Timing Symbol Parameter t Asynchronous 1 Reset Pulse Width t Reset Completion to 2 Normal Operation Delay 11.0 Reset Timing RXRD_TXWR TXC RXC t 1 RESET RXRDEN TXWREN MD400152/E Fast Ethernet Controller Min. Typ. Max ...
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Ordering Information PACKAGE TYPE PLASTIC QUAD FLATPACK 208 Pin PQFP SEEQ Hurricane, Full Duplex Designation SEEQ’s Hurricane family of products offer 100MBit Fast Ethernet Solu- tions. Symbol indentifies product as a part of SEEQ’s Hurricane family. TM HURRICANE Revision History ...
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Revision History Page Sections: CRC Error Counter, Runt Frame Counter, Alignment Error Counter, Transmit Collision Counter Receive Collision Counter; copy has changed ... To read this counter, two consecutive reads need to be performed to the same ...
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Revision History 2/6/97 2/6/97 - Document revision changed to MD400152/D. Page 2, 5.0 AC Characteristics has been changed to 5.0 Command/Status Interface Timing. Page 14, Section, 3.2.2 Transmission Initiation/Deferral has been changed to 3.2.2 Transmission Initiation in Full Duplex and ...
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Revision History Page 42, 9.0 Transmit Data Interface Timing on Exception Conditions - t INT HIGH (Min) reference has been changed to 3ns INT HIGH (Max) reference has been changed to ...
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Revision History 3/19/98 Document Revision change to MD400152/E Page 2 - Table of Contents Reference to 11.0 Reset Timing added. Page 50 - 11.0 Reset Timing Table and Timing Diagram added. MD400152/E Fast Ethernet Controller 55 4-55 84C300A 4-Port ...
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... QQ84C300A #208 #1 0.20 ± 0.10 1. All dimensions are in (millimeters). MD400152/E 208 Pin PQFP 30.60 ± 0.30 28.00 ± 0.20 1.25 0.50 Detail A 56 4-56 84C300A 4-Port Fast Ethernet Controller 0.15 ±0.10 –0.05 0.10 MAX See Detail A 0.25 min. 3.40 ± 0.20 4.10 Max 8° 0.50 ± 0.20 ...