S-93A56AD0A-J8T2GB Seiko, S-93A56AD0A-J8T2GB Datasheet
S-93A56AD0A-J8T2GB
Available stocks
Related parts for S-93A56AD0A-J8T2GB
S-93A56AD0A-J8T2GB Summary of contents
Page 1
... High-temperature operation: Lead-free products Packages Package name 8-Pin SOP (JEDEC) Caution Before using the product in medical equipment or automobile equipment including car audios, keyless entries and engine control units, contact to SII is indispensable. The S-93A46A/56A/66A operation, high speed, low current consumption bit, 2 K-bit and 4 K-bit serial E operating voltage range ...
Page 2
... S-93A46A/56A/66A Pin Assignment 8-Pin SOP (JEDEC) Top view Figure 1 S-93A46AD0A-J8T2GB (Dynamic burn-in) S-93A56AD0A-J8T2GB (Dynamic burn-in) S-93A66AD0A-J8T2GB (Dynamic burn-in) S-93A46AD0A-J8T2GD (Wafer burn-in) S-93A56AD0A-J8T2GD (Wafer burn-in) S-93A66AD0A-J8T2GD (Wafer burn-in) 2 Pin No. Pin name 1 VCC TEST 4 5 GND 6 ...
Page 3
... ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter Address Memory array decoder Data register ...
Page 4
... ERASE (Erase data) WRAL (Write all) ERAL (Erase all) EWEN (Write enable) EWDS (Write disable) *1. When the 16-bit data in the specified address has been output, the data in the next address is output. Remark x: Doesn’t matter 3. S-93A66A Instruction Start Bit SK input clock ...
Page 5
... Input voltage Output voltage Operating ambient temperature Storage temperature Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Item Power supply voltage ...
Page 6
... CMOS SERIAL E PROM S-93A46A/56A/66A Endurance Item Endurance *1. For each address (Word: 16 bits) DC Electrical Characteristics Item Current consumption (READ) Item Current consumption (WRITE) Item Symbol Standby current CS GND, DO Open consumption Other inputs to V Input leakage current Output leakage ...
Page 7
... Clock frequency Clock pulse width Output disable time Output enable time *1. The clock cycle of the SK clock (frequency several AC characteristics aware that even if the SK clock cycle time is minimized, the clock cycle (1/f ) cannot be made to equal t SK Parameter Write time Table 12 Test Conditions Input pulse voltage 0 ...
Page 8
... Hi (READ) Hi-Z DO (VERIFY) *1. Indicates high impedance. *2. 1/f is the SK clock cycle. This clock cycle is determined by a combination of several AC SK characteristics aware that even if the SK clock cycle time is minimized, the clock cycle (1/f cannot be made to equal 1 SKH SKL ...
Page 9
... CDS invalid and no instructions are allowed. Start Bit A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit is not recognized even if the SK pulse is input as long as the DI pin is low. 1. Dummy Clock SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial memory operation ...
Page 10
... After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the last input address (A impedance (Hi-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of SK. 3.1 Sequential Read ...
Page 11
... Caution 1. Input a low level to the DI pin during a verify operation high level is input to the DI pin at the rise of SK when the output status of the DO pin is high, the S-93A66A latches the instruction assuming that a start bit has been input ...
Page 12
... The write operation starts when CS goes low. There is no need to set the data to 1 before writing. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer to “ ...
Page 13
... Erasing Data (ERASE) To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input the ERASE instruction and address following the start bit. There is no need to input data. The data erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer to “ ...
Page 14
... WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write operation starts when CS goes low. There is no need to set the data to 1 before writing. When the clocks more than the specified number been input, the clock pulse monitoring circuit cancels the WRAL instruction. For details of the clock pulse monitoring circuit, refer to “ ...
Page 15
... Erasing Chip (ERAL) To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then input the ERAL instruction and an address following the start bit. Any address can be input. There is no need to input data. The chips erase operation starts when CS goes low. When the clocks more than the specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For details of the clock pulse monitoring circuit, refer to “ ...
Page 16
... The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is disabled is called the program disable mode. After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address (optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been input ...
Page 17
... WRAL, and ERAL) are cancelled, and the write disable state (EWDS) is automatically set. The detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of about 0.3 V (Refer to Figure 16 ). Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE, ERASE, WRAL, or ERAL) is executed ...
Page 18
... The S-93A46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an erroneous clock count caused by the application of noise pulses or double counting of clocks. Instructions are cancelled if a clock pulse whose count other than the one specified for each write instruction (WRITE, ERASE, WRAL, or ERAL) is detected. < ...
Page 19
... DO pins, and a 3-wire interface that connects the DI input pin and DO output pin. When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins of the S-93A46A/56A/66A via a resistor (10 k the CPU takes precedence in being input to the DI pin (Refer to “ ...
Page 20
... CMOS SERIAL E PROM S-93A46A/56A/66A 2.1 Input Pin Figure 19 CS Pin Figure 20 SK Pin Figure 21 DI Pin Seiko Instruments Inc. Rev.2.1 _00 ...
Page 21
... Input Pin Noise Elimination Time The S-93A46A/56A/66A includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width less can be eliminated. Note, therefore, that noise with a pulse width of more than 20 ns will be recognized as a pulse if the ...
Page 22
... V Ta= =100 kHz, 10 kHz SK DATA=0101 0.4 I CC1 (mA) 0.2 100 kHz 10 kHz ( 1.2 Current consumption (READ) I CC1 vs. ambient temperature Ta 0.4 I CC1 (mA) 0.2 0 1.4 Current consumption (READ) I CC1 vs. power supply voltage V 0.4 I CC1 (mA) 0.2 0 1.6 Current consumption (READ) I CC1 vs. Clock frequency ...
Page 23
... CC2 (mA) 0.5 0 –40 0 125 1.9 Current consumption (WRITE) I vs. ambient temperature 1.0 I CC2 (mA) 0.5 0 –40 0 125 1.11 Current consumption in standby mode I vs. ambient temperature CS=GND 1 0.5 0 –40 0 125 1.8 Current consumption (WRITE) I CC2 vs. ambient temperature Ta V 1.0 I CC2 (mA) 0 ...
Page 24
... 1.14 Input leakage current 1.16 Output leakage current 1.18 High-level output voltage (V) Seiko Instruments Inc. LI vs. ambient temperature CS, SK, DI, TEST=5.5 V 1.0 0.5 0 –40 0 125 vs. ambient temperature DO=5.5 V 1.0 0.5 0 –40 0 125 ...
Page 25
... Rev.2.1 _00 1.19 High-level output voltage V vs. ambient temperature =– 2 2.6 (V) 2.4 0 125 – 1.21 Low-level output voltage V vs. ambient temperature =100 0.02 (V) 0.01 0 –40 0 125 1.23 High-level output current I vs. ambient temperature – ...
Page 26
... PROM S-93A46A/56A/66A 1.25 Low-level output current I vs. ambient temperature (mA –40 0 125 1.27 High-level input voltage V vs. power supply voltage V Ta= (V) CC 1.29 High-level input voltage V vs. power supply voltage V Ta= ...
Page 27
... 1.32 Low-level input voltage V IL vs. ambient temperature (V) 1.34 Low-level input voltage V IL vs. ambient temperature (V) 1.36 Low supply voltage release voltage V DET vs. ambient temperature Ta 2.0 +V DET (V) 1.0 Seiko Instruments Inc. CMOS SERIAL E S-93A46A/56A/66A =5 CS –40 0 ...
Page 28
... CMOS SERIAL E PROM S-93A46A/56A/66A 2. AC Characteristics 2.1 Maximum operating frequency f vs. power supply voltage V Ta= max. (Hz) 100 (V) CC 2.3 Write time t PR vs. ambient temperature (ms) 2.0 0 –40 0 125 2.5 Write time t PR vs. ambient temperature ...
Page 29
... Rev.2.1 _00 2.7 Data output delay time t vs. ambient temperature 0.4 (ns) 0.2 0 –40 0 125 2.8 Data output delay time (ns) Seiko Instruments Inc. CMOS SERIAL E S-93A46A/56A/66A PD vs. ambient temperature 1.5 1.0 0.5 0 –40 0 125 PROM 29 ...
Page 30
... CMOS SERIAL E PROM S-93A46A/56A/66A Product Name Structure S-93AxxA J8T2 Burn-in specification B: Dynamic burn-in D: Wafer burn-in Package code and IC packing specifications J8T2: 8-Pin SOP (JEDEC), Tape Operation temperature A: 40 125 C Fixed Pin assignment Product name S-93A46A: 1 K-bit S-93A56A: 2 K-bit S-93A66A: 4 K-bit Seiko Instruments Inc ...
Page 31
...
Page 32
...
Page 33
...
Page 34
... Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc ...