SM5844AF Seiko, SM5844AF Datasheet
SM5844AF
Related parts for SM5844AF
SM5844AF Summary of contents
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... LSI. It reads 16 or 20-bit word length input data, and writes 16, 18, or 20-bit word length output data. It also features a built-in digital deemphasis filter and digital attenuator. The SM5844AF operates from supply, and is available in 44-pin QFPs. FEATURES Functions Left/right-channel processing (stereo) Input sample rate (fsi) ranges • ...
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... Output S/N ratio (theoretical values) S/N ratio Output signal word 16-bit input word 20-bit input word length length 16 bits 94 bits 97 bits 97.7 dB SM5844AF Interfaces Input data format • 2s-complement, L/R alternating, serial • Normal format (non IIS ord length 1 16 bits bits 4 ...
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... OW18N Output format OW20N controller IISN Output-stage SLAVE clock select OCLK Output-stage divider OCKSL THRUN DMUTE Mute generator SM5844AF IFM1 IFM2 BCKI Input data interface Arithmetic operations Deemphasis operation Attenuator Interpolation filter operation Output operation Dither Output data interface ...
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... Output dither control. Dither ON when LOW , and OFF when HIGH Test pin. Test mode when LOW . Normal operating mode when HIGH. SM5844AF Description ord length Data sequence bits ...
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... P arameter Supply voltage range Input voltage range Storage temperature range Pow er dissipation Soldering temperature Soldering time Recommended Operating Conditions arameter Supply voltage range Operating temperature range SM5844AF Description Rating V 0 125 ...
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... pulsewidth HIGH-level clock pulsewidth Clock pulse cycle ICLK and OCLK timing ICLK OCLK t CWH SM5844AF Condition 5.0 V – 0. – 1.0 mA – ...
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... HIGH-level pulsewidth pulse cycle Last BCKO rising edge to LRCO edge LRCO edge to first BCKO rising edge clock inputs exceeding 64fso cannot be detected, and will cause incorrect operation. SM5844AF Rating typ t 50 – ...
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... MLEN hold time -level pulsewidth MLEN HIGH-level pulsewidth 1. t and t are the input waveform transition times measured between 0. MDT, MCK, MLEN timing MDT t MDS MCK MLEN SM5844AF t BCY2 t t BCWH2 BCWL2 t BL2 Rating typ t – ...
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... DOUT and LRCO delay time SLAVE = HIGH (inputs arameter DOUT delay time SM5844AF Rating typ t – – – – f Rating ...
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... DOUT, BCKO, LRCO timing OCLK BCKO sbL1 sbL2 t BOWH BCKO bdH bdL DOUT t bdH LRCO t LOCH SM5844AF sbH1 sbH2 t BOWL t BOCY t bdL t LOCL t LROOY NIPPON PRECISION CIRCUITS—10 ...
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... Deemphasis filter frequency characteristic Phase 100 SM5844AF 48k 44.1k 44.1k 32k 0.400 0.450 0.500 0.550 Frequency (fs) 48.0 kHz 44.1 kHz 32 kHz 48.0, 44.1 and 32 kHz Attenuation 200 500 1k 2K Frequency (Hz) NIPPON PRECISION CIRCUITS—11 Up conversion ...
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... When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control flag data. When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function. SM5844AF Data W ord length Data position ...
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... HIGH Not used MCK MLEN Figure 2. Mode flag data format (B1 = HIGH) SM5844AF latched into the mode register on the rising edge of the latch enable clock MLEN. The mode register addressed is determined by the 1st bit of the 12 data bits before MLEN goes HIGH. If this bit is LOW, then the data is read into the attenuation data register as shown in fi ...
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... SM5844AF Mode function select Select ...
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... 60.206 12.041 0.0085 400H (to 7FFH) 0 SM5844AF When the leading bit is 0 (B1 = LOW), the following 11 bits are read into the attenuation register and used as an unsigned integer in MSB first format. See figure ...
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... The time taken to reduce the gain from 0 dB ( (1024/fso), which corresponds to approximately 23.2 ms when fso = 44.1 kHz. Level Level 3 Gain Level 2 t Level 4 Figure 4. Attenuator operation example SM5844AF Level 5 Time NIPPON PRECISION CIRCUITS—16 ...
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... 20th Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output. SM5844AF automatically selected for output. Output data is in 20-bit front-packed format. Content 9 1.0 times 2.0 times (1/2 conversion rate ratio) 0.5 times (2.0 conversion rate ratio) Selected fi ...
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... RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after LRCI and ICLK have stabilized. SM5844AF Output system clock (OCLK, OCKSL) The output system clock can be set to run at either 256fso or 384fso, where fso is the input frequency on LRCO ...
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... bits IIS bits SM5844AF Output Timing Calculation The output timing is calculated to maintain the desired ratio between the output data cycle and the input data cycle. Filter Characteristic Selection Conversion rates from 0.5 to 2.0 times are supported using the following 4 filter types. ...
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... Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW) Left-channel data MSB BCKI LRCI All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required. SM5844AF 1/fs Left-channel data LSB MSB 1/fs ...
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... Audio data output timing (rear-packed 18-bit word) Left-channel data MSB DOUT 1 2 BCKO LRCO Audio data output timing (rear-packed 20-bit word) Left-channel data MSB DOUT 1 2 BCKO LRCO SM5844AF 1/fs Left-channel data MSB LSB 1/fso Right-channel data LSB MSB ...
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... State data output timing (IISN = HIGH) State data MSB STATE 1 2 BCKO LRCO State data output timing (IISN = LOW) State data MSB STATE 1 2 BCKO LRCO SM5844AF 1/fso Right-channel data LSB MSB 1/fso Right-channel data LSB MSB ...
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... OUTPUT 1/fs LRCI Serial data input t input LRCO 1/fso t INPUT SM5844AF been read out completely (on the rising edge of LRCO). The delay between input and output is given (49 ± 2)/fsi. OUTPUT INPUT 49 ±2 Serial data output t – ...
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... Digital audio interface transceiver(YM3613) OCKSL OCLK LRCO BCKO DOUT SM5844AF IISN OW18N OW20N THRUN SLAVE SM5844AF 384fs ICLK ICKSL LRCI BCKI SM5844AF DI MCOM MLEN/DEEM MDT/FSI1 MCK/FSI2 384fs 16.9344 MHz øA WCI BCI DIN DIT YM3613 SEL NIPPON PRECISION CIRCUITS—24 1FM1 1FM2 ...
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... OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N LRCO BCKO DOUT 100ns 354ns SM5844AF When tbdH2, tbdL2 is maximum 100ns, ideal timing may not be attained for the following devise, depending on the OCLK cycle (example 1). Please use considering the timing in the following examples in the slave mode. ...
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... Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS LTD. SM5844AF NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan ...