AM29LV065DU90RWHI Meet Spansion Inc., AM29LV065DU90RWHI Datasheet
AM29LV065DU90RWHI
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AM29LV065DU90RWHI Summary of contents
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Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these ...
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Am29LV065D 64 Megabit ( 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 3.0 to 3.6 volt read, erase, and program operations ■ VersatileIO TM control — Device generates ...
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GENERAL DESCRIPTION The Am29LV065D Mbit, 3.0 Volt (3 3.6 V) single power supply flash memory devices orga- nized as 8,388,608 bytes. Data appears on DQ0-DQ7. The device is designed to be programmed in-system with the ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number V = 3.0–3 Speed Option V = 3.0–3 Max Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM ...
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CONNECTION DIAGRAMS NC 1 A22 2 A16 3 4 A15 A14 5 A13 6 7 A12 A11 WE# 12 RESET# 13 ACC 14 RY/BY# 15 A18 ...
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CONNECTION DIAGRAMS A8 B8 NC* NC A14 A13 NC* NC WE# RESET RY/BY# ACC C3 A7 A18 NC Balls are shorted together via ...
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PIN DESCRIPTION A0–A22 = 23 Addresses inputs DQ0–DQ7 = 8 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input ACC = Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV065D U 90R WH DEVICE NUMBER/DESCRIPTION Am29LV065D 64 Megabit ( ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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TM See “VersatileIO (V ) Control” for more information. IO Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I ...
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If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t (during Embedded Algorithms). The sys- READY tem can thus ...
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Table 2. Sector Address Table (Continued) Sector A22 A21 SA27 0 0 SA28 0 0 SA29 0 0 SA30 0 0 SA31 0 0 SA32 0 1 SA33 0 1 SA34 0 1 SA35 0 1 SA36 0 1 SA37 ...
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Table 2. Sector Address Table (Continued) Sector A22 A21 SA62 0 1 SA63 0 1 SA64 1 0 SA65 1 0 SA66 1 0 SA67 1 0 SA68 1 0 SA69 1 0 SA70 1 0 SA71 1 0 SA72 ...
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Table 2. Sector Address Table (Continued) Sector A22 A21 SA97 1 1 SA98 1 1 SA99 1 1 SA100 1 1 SA101 1 1 SA102 1 1 SA103 1 1 SA104 1 1 SA105 1 1 SA106 1 1 SA107 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same ...
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Temporary Sector Group Unprotect (Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4)). This feature allows temporary unprotection of previ- ously protected sector groups to ...
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START PLSCNT = 1 RESET Wait 1 μs Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes Set up sector group address Sector Group Protect: Write 60h to sector group address with A6 = ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 μs protected. Write 60h to any address Remove V from RESET# Write 40h to SecSi ...
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Addresses (x8) Data 10h 51h 11h 52h 12h 59h 13h 02h 14h 00h 15h 40h 16h 00h 17h 00h 18h 00h 19h 00h 1Ah 00h Addresses (x8) Data 1Bh 27h 1Ch 36h 1Dh 00h 1Eh 00h 1Fh 04h 20h 00h ...
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Table 9. Primary Vendor-Specific Extended Query Addresses (x8) Data 40h 50h 41h 52h 42h 49h 43h ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 10 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper ...
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Table 10 and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip ...
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After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program ...
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Command Definitions Table 10. Am29LV065D Command Definitions Command Sequence (Note 1) Addr Read (Note Reset (Note 6) 1 XXX Manufacturer ID 4 XXX Device ID 4 XXX SecSi Sector Factory 4 XXX Protect (Note 8) Sector Group ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6 each ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description I Input Load Current LI I A9, ACC Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current ...
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DC CHARACTERISTICS Zero-Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 10. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 12. Test Setup 3.0 V 1.5 V Input 0.0 V Note < the input measurement reference level is 0.5 V ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 2) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses XXXh CE# OE# WE Data RY/BY VCS Note program address program data ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses XXXh CE Data 55h RY/BY# t VCS V CC Note sector address (for Sector Erase Valid Address ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR ID RESET# Setup Time for Temporary Sector t RSP Unprotect RESET# Hold Time from RY/BY# High for t RRB Temporary Sector Group ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector group protect For sector group ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS XXX for program XXX for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Program Time Accelerated Byte Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3 programming typicals ...
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PHYSICAL DIMENSIONS TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP) 50 Dwg rev AA; 10/99 Am29LV065D February 16, 2006 ...
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PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA package February 16, 2006 Am29LV065D Dwg rev AF; 10/99 51 ...
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REVISION SUMMARY Revision A (July 27, 2000) Initial release. Revision A+1 (August 4, 2000) Global Deleted references to the 48-pin reverse TSOP. Connection Diagrams Corrected pin 36 on TSOP package to V Accelerated Program Operation, Unlock Bypass Command Sequence Modified ...
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Byte Program Command Sequence, Chip Erase Command Sequence, Erase Suspend/Erase Resume Commands Added - The Secsi Sector, autoselect, and CFI func- tions are not available when a program function is in progress. DC Characteristics - CMOS Compatible Removed I . ...
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Am29LV065D February 16, 2006 ...