IN74HC125AD Integral Corp., IN74HC125AD Datasheet

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IN74HC125AD

Manufacturer Part Number
IN74HC125AD
Description
Quad 3-state noninverting buffer high-performance silicon-gate CMOS
Manufacturer
Integral Corp.
Datasheet
TECHNICAL DATA
Quad 3-State Noninverting Buffers
High-Performance Silicon-Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
state memory address drivers, clock drivers, and other bus-oriented
systems. The devices have four separate output enables that are active-low.
118
The IN74HC125A is identical in pinout to the LS/ALS125. The device
The IN74HC125A noninverting buffers are designed to be used with 3-
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 7 = GND
PIN 14 =V
CC
T
X = don’t care
Z = high impedance
FUNCTION TABLE
A
ORDERING INFORMATION
PIN ASSIGNMENT
= -55 to 125 C for all packages
A
H
X
L
Inputs
IN74HC125A
IN74HC125AN Plastic
IN74HC125AD SOIC
OE
H
L
L
Output
Y
H
L
Z

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IN74HC125AD Summary of contents

Page 1

... Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices LOGIC DIAGRAM PIN 14 =V PIN 7 = GND 118 CC IN74HC125A ORDERING INFORMATION IN74HC125AN Plastic IN74HC125AD SOIC T = -55 to 125 C for all packages A PIN ASSIGNMENT FUNCTION TABLE Inputs Output ...

Page 2

MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin Output Current, per ...

Page 3

IN74HC125A DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low - IL Level Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input IN Leakage Current I Maximum ...

Page 4

AC ELECTRICAL CHARACTERISTICS Symbol Parameter Maximum Propagation Delay, Input A to PLH PHL Output Y (Figures 1 and Maximum Propagation Delay, Output Enable toY PLZ PHZ (Figures 2 and ...

Page 5

IN74HC125A Figure 3. Test Circuit 122 EXPANDED LOGIC DIAGRAM (1/4 of the Device) Figure 4. Test Circuit ...

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