IS61LV6432-5TQ Integrated Silicon Solution, IS61LV6432-5TQ Datasheet

no-image

IS61LV6432-5TQ

Manufacturer Part Number
IS61LV6432-5TQ
Description
64K x 32 synchronous pipeline static RAM
Manufacturer
Integrated Silicon Solution
Datasheet
IS61LV6432
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Pentium™ or linear burst sequence control
• Three chip enables for simple depth expansion
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• 3.3V V
• Two Clock enables and one Clock disable to
• Control pins mode upon power-up:
• Industrial temperature available
This document contains PRELIMINARY data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product.
We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
PRELIMINARY SR018-1C
06/01/98
IS61LV6432
64K x 32 SYNCHRONOUS
PIPELINE STATIC RAM
FAST ACCESS TIME
control
using MODE input
and address pipelining
eliminate multiple bank bus contention.
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GND
or V
Symbol
t
t
KQ
KC
CCQ
CC
to alter their power-up state
and 2.5V V
Parameter
CLK Access Time
Cycle Time
Frequency
CCQ
for 2.5 I/O's
-166
166
5
6
Q
DESCRIPTION
The
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 65,536
words by 32 bits, fabricated with
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQ17-DQ24,
by
to be written.
Bursts can be initiated with either
Processor) or
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV6432 and controlled by the
address advance) input pin.
Asynchronous signals include output enable (
input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH
input on the ZZ pin puts the SRAM in the power-down state.
When ZZ is pulled LOW (or no connect), the SRAM normally
operates after three cycles of the wake-up period. A LOW
input, i.e., GND
(or no connect) on MODE pin selects INTERLEAVED Burst.
-133
133
7.5
BWE
5
ISSI
controls DQ1-DQ8,
being LOW. A LOW on
IS61LV6432 is a high-speed, low-power synchro-
-117
117
8.5
5
ADSC
Q
, on MODE pin selects LINEAR Burst. A V
100
10
(Address Status Cache Controller) input
-5
5
BW4
controls DQ25-DQ32, conditioned
BW2
12
83
-6
6
GW
controls DQ9-DQ16,
input would cause all bytes
ISSI
ADSP
13
75
-7
7
's advanced CMOS
MAY 1998
ISSI
(Address Status
OE
15
66
-8
8
), sleep mode
ADV
ISSI
(burst
MHz
Unit
BW3
ns
ns
CCQ
®
®
1

Related parts for IS61LV6432-5TQ

IS61LV6432-5TQ Summary of contents

Page 1

... ADSC Processor) or (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated inter- nally by the IS61LV6432 and controlled by the address advance) input pin. Asynchronous signals include output enable ( input (ZZ), clock (CLK) and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. ...

Page 2

... IS61LV6432 BLOCK DIAGRAM CLK ADV ADSC ADSP 16 A15-A0 GW BWE BW4 BW3 BW2 BW1 CE1 CE2 CE3 OE 2 MODE A0' Q0 CLK A0 BINARY COUNTER A1 CLR ADDRESS REGISTER CE CLK DQ32-DQ25 BYTE WRITE REGISTERS CLK D Q DQ24-DQ17 BYTE WRITE REGISTERS ...

Page 3

... IS61LV6432 PIN CONFIGURATION 100-Pin TQFP and PQFP (Top View) 100 DQ17 3 DQ18 4 VCCQ 5 GNDQ 6 DQ19 7 DQ20 8 DQ21 9 DQ22 10 GNDQ 11 VCCQ 12 DQ23 13 DQ24 14 VCCQ 15 VCC GND 18 DQ25 19 DQ26 20 VCCQ 21 GNDQ ...

Page 4

... IS61LV6432 TRUTH TABLE Address Operation Used Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Deselected, Power-down None Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Begin Burst External ...

Page 5

... IS61LV6432 INTERLEAVED BURST ADDRESS TABLE (MODE = V External Address 1st Burst Address LINEAR BURST ADDRESS TABLE (MODE = GND A1', A0' = 1,1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) ...

Page 6

... IS61LV6432 OPERATING RANGE Range Ambient Temperature Commercial +70 C Industrial – + ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current LI I Output Leakage Current LO POWER SUPPLY CHARACTERISTICS ...

Page 7

... IS61LV6432 (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions MHz, Vcc = 3.3V TEST CONDITIONS Parameter Input Pulse Level for Input Pins Input Pulse Level for I/O Pins ...

Page 8

... IS61LV6432 READ CYCLE SWITCHING CHARACTERISTICS -166 Symbol Parameter Min. Max. t Cycle Time Clock High Time 2.4 — Clock Low Time 2.4 — Clock Access Time — (2) Clock High to Output Invalid 1.5 — KQX (2,3) t Clock High to Output Low-Z 0 KQLZ (2,3) t Clock High to Output High-Z 1 ...

Page 9

... IS61LV6432 READ CYCLE TIMING: PIPELINE t KC CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ ...

Page 10

... IS61LV6432 WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time CES t Address Advance Setup Time ...

Page 11

... IS61LV6432 WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV A15-A0 WR1 BWE t WS BW4-BW1 WR1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 OE High-Z DATA ...

Page 12

... IS61LV6432 READ/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (2) Clock High to Output Invalid KQX (2,3) t Clock High to Output Low-Z KQLZ (2,3) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 13

... IS61LV6432 READ/WRITE CYCLE TIMING: PIPELINE CLK ADSP t SS ADSC ADV A15-A0 RD1 BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t KQ ...

Page 14

... IS61LV6432 SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Time KH t Clock Low Time KL t Clock Access Time KQ t (4) Clock High to Output Invalid KQX (4,5) t Clock High to Output Low-Z KQLZ (4,5) t Clock High to Output High-Z KQHZ t Output Enable to Output Valid ...

Page 15

... IS61LV6432 SNOOZE AND RECOVERY CYCLE TIMING CLK ADSP ADSC ADV A15-A0 RD1 GW BWE BW4-BW1 t t CES CEH CE1 t t CES CEH CE2 t t CES CEH CE3 t OEQ OE t OELZ High-Z DATA OUT t KQLZ t High-Z DATA IN ZZ Single Read Integrated Silicon Solution, Inc ...

Page 16

... TQFP 75 PQFP TQFP 66 PQFP TQFP PQFP TQFP PQFP NOTICE Integrated Silicon Solution, Inc. ISSI Order Part Number Package IS61LV6432-117TQI TQFP IS61LV6432-117PQI PQFP IS61LV6432-5TQI TQFP IS61LV6432-5PQI PQFP IS61LV6432-6TQI TQFP IS61LV6432-6PQI PQFP IS61LV6432-7TQI TQFP IS61LV6432-7PQI PQFP IS61LV6432-8TQI TQFP IS61LV6432-8PQI PQFP ISSI ® 2231 Lawson Lane ...

Related keywords